Analysis of reliability of flip-flops under transistor aging effects in nano-scale CMOS technology

Author(s):  
Vikram G Rao ◽  
Hamid Mahmoodi
2012 ◽  
Vol 4 (9) ◽  
pp. 924-929 ◽  
Author(s):  
Si Han Cao ◽  
Xiao Peng Yu ◽  
Yun Pan ◽  
Zheng Shi ◽  
Chang Hui Hu

2016 ◽  
Vol 67 ◽  
pp. 74-81 ◽  
Author(s):  
Basel Halak ◽  
Vasileios Tenentes ◽  
Daniele Rossi

2011 ◽  
Vol 9 ◽  
pp. 225-230
Author(s):  
S. More ◽  
M. Fulde ◽  
F. Chouard ◽  
D. Schmitt-Landsiedel

Abstract. This paper discusses reliability analysis of a buffer circuit targeted for an analog to digital converter application. The circuit designed in a 32 nm high-κ metal gate CMOS technology was investigated by circuit simulation and sensitivity analysis. This analysis was conducted for realistic time varying (AC) stress. As aging effects, negative and positive bias temperature instability, conducting and non-conducting hot carrier injection are taken into consideration. The aging contributions of these effects on the different transistors in the buffer circuit and on different buffer performance figures are evaluated. Using these results, the impact of an aged buffer circuit on the performance of a successive approximation ADC circuit is evaluated. The most severely affected performance due to aging is amplifier offset, which leads to time varying gain error in the ADC circuit.


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