Work-function engineering in gate first technology for multi-VT dual-gate FDSOI CMOS on UTBOX

Author(s):  
O. Weber ◽  
F. Andrieu ◽  
J. Mazurier ◽  
M. Casse ◽  
X. Garros ◽  
...  
Keyword(s):  
Author(s):  
Ms. Aishwarya Tomar

This paperwork includes a tunnelling transistor with dual gate and employing the use of dielectric modulation (DG-DM-JL-TFET) based structure. In order to recognize the biomolecule like protein, biotin, uricase etc a nano cavity is presented above the tunnelling. Charge plasma technique is used to form the drain and source regions into the substrate. High work function creates a hole in source and similarly a lower work function will create an electron in drain. The “N” region is etched into the substrate using hafnium electrode with a work function of 3.9 eV. Si02 of 0.5nm thickness is inserted between electrode of source. The “P+” region is etched on intrinsic silicon substrate using Platinum electrode having a work function of 5.93 eV. The device structure proposed in this paper shows results for sensitivity for charged and neutral biological molecules. The sensitivity of the biological molecules having higher dielectric constant is greater than those biological molecules possessing lower dielectric constant.


Author(s):  
H.H. Rotermund

Chemical reactions at a surface will in most cases show a measurable influence on the work function of the clean surface. This change of the work function δφ can be used to image the local distributions of the investigated reaction,.if one of the reacting partners is adsorbed at the surface in form of islands of sufficient size (Δ>0.2μm). These can than be visualized via a photoemission electron microscope (PEEM). Changes of φ as low as 2 meV give already a change in the total intensity of a PEEM picture. To achieve reasonable contrast for an image several 10 meV of δφ are needed. Dynamic processes as surface diffusion of CO or O on single crystal surfaces as well as reaction / diffusion fronts have been observed in real time and space.


Author(s):  
S. G. Ghonge ◽  
E. Goo ◽  
R. Ramesh ◽  
R. Haakenaasen ◽  
D. K. Fork

Microstructure of epitaxial ferroelectric/conductive oxide heterostructures on LaAIO3(LAO) and Si substrates have been studied by conventional and high resolution transmission electron microscopy. The epitaxial films have a wide range of potential applications in areas such as non-volatile memory devices, electro-optic devices and pyroelectric detectors. For applications such as electro-optic devices the films must be single crystal and for applications such as nonvolatile memory devices and pyroelectric devices single crystal films will enhance the performance of the devices. The ferroelectric films studied are Pb(Zr0.2Ti0.8)O3(PLZT), PbTiO3(PT), BiTiO3(BT) and Pb0.9La0.1(Zr0.2Ti0.8)0.975O3(PLZT).Electrical contact to ferroelectric films is commonly made with metals such as Pt. Metals generally have a large difference in work function compared to the work function of the ferroelectric oxides. This results in a Schottky barrier at the interface and the interfacial space charge is believed to responsible for domain pinning and degradation in the ferroelectric properties resulting in phenomenon such as fatigue.


1993 ◽  
Vol 3 (9) ◽  
pp. 1719-1728
Author(s):  
P. Dollfus ◽  
P. Hesto ◽  
S. Galdin ◽  
C. Brisset

1994 ◽  
Vol 164 (4) ◽  
pp. 375 ◽  
Author(s):  
B.V. Vasil'ev ◽  
M.I. Kaganov ◽  
V.L. Lyuboshits

2009 ◽  
Vol 129 (6) ◽  
pp. 1169-1175 ◽  
Author(s):  
Michiko Yoshitake ◽  
Shinjiro Yagyu
Keyword(s):  

Author(s):  
Cheng-Piao Lin ◽  
Chin-Hsin Tang ◽  
Cheng-Hsu Wu ◽  
Cheng-Chun Ting

Abstract This paper analyzes several SRAM failures using nano-probing technique. Three SRAM single bit failures with different kinds of Gox breakdown defects analyzed are gross function single bit failure, data retention single bit failure, and special data retention single bit failure. The electrical characteristics of discrete 6T-SRAM cells with soft breakdown are discussed and correlated to evidences obtained from physical analysis. The paper also verifies many previously published simulation data. It utilizes a 6T-SRAM vehicle consisting of a large number of SRAM cells fabricated by deep sub-micron, dual gate, and copper metallization processes. The data obtained from this paper indicates that Gox breakdown location within NMOS pull-down device has larger a impact on SRAM stability than magnitude of gate leakage current, which agrees with previously published simulation data.


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