An approach on underfill material selection for the low-k Flip Chip Plastic Ball Grid Array (FCPBGA)

Author(s):  
Zainudin Kornain ◽  
Nowshad Amin ◽  
Ang Ye Cheah ◽  
Azman Jalar
Author(s):  
K. Ramakrishna ◽  
T.-Y. Tom Lee

Flip-chip plastic ball grid array (FC-PBGA) packages are fast becoming the industry norm, in particular in the performance and cost driven consumer electronics sector. Since high thermal conductivity (k∼15–20 W/(m K)) ceramic substrate is replaced by a low conductivity (k∼0.2–0.5 W/(m K)) organic substrate in the FC-PBGA packages, enhancement of thermal performance of these packages to meet ever increasing demands is crucial for their wide spread use. In this study, enhancements to thermal performance of FC-PBGA packages due to material and design changes and external means such as heat spreaders and overmolding of the packages have been evaluated by solving a conjugate heat transfer models using the methods of computational fluid dynamic. The thermal enhancements evaluated in this study include the effect of thermal conductivity of the chip to package interconnect due to change in underfill material and the C4 bump pitch, effect of package to printed wiring board (PWB) interconnection through the use of thermal balls, effect of a heat spreader on the backside of the die, and overmolding the die without and with a heat spreader. Thermal performance of the FC-PBGA packages have been studied using junction to ambient thermal resistance, Θja, junction-to-board thermal resistance Ψjb, and junction to case thermal resistance ΨjT under natural and forced convection for freestream velocities up to 2 m/s and the for following ranges of parameters: Substrate size: 25 to 35 mm, die size: 6.19×7.81 mm (48 mm2 area) and 9.13×12.95 mm (118 mm2 area), C4 pitch: 250 mm, 150 mm and below, underfill material thermal conductivity: 0.6 to 3.0 W/(m K), no thermal balls between the package and the PWB to 9×9 array of thermal balls on 1.27 mm square pitch, and with copper heat spreader on the back of the bare and overmolded die. Based on previous experience, predictions in this study are expected to be within ±10% of measured data. The following conclusions are drawn from this study: 1. It is concluded that the thermal conductivity of the underfill materials in the range 0.6 to 10 W/(m K) is negligible. 2. It is also concluded that the bump pitch can decrease thermal resistances by 12 to 15 %. The change may be smaller with large die area. 3. Thermal balls (C5) connected to the PTHs in the PWB can decrease thermal resistance by about 10% to 15% as the number of thermal balls & PTHs increase zero to 9×9 on 1.27 mm pitch. The effect die size on this thermal enhancement is more noticeable on Ψjb. 4. Heat spreader on the back of the die decreases Θja by a small amount (6–7%) in natural convection and a large amount, about 25% in forced convection. 5. Overmolded die with heat spreader on the top of the overmold provides better thermal enhancement than heat spreader alone up to about 1 m/s. Beyond 1 m/s, heat spreader (without overmold) performs slightly better.


Author(s):  
Nicholas Kao ◽  
Jeng Yuan Lai ◽  
Jase Jiang ◽  
Yu Po Wang ◽  
C. S. Hsiao

With the trend of electronic consumer product toward more functionality, high performance and miniaturization, IC chip is required to deliver more I/Os signals and better electrical characteristics under same package form factor. Thus, Flip Chip BGA (FCBGA) package was developed to meet those requirements offering better electrical performance, more I/O pins accommodation and high transmission speed. For high-speed application, the low dielectric constant (low-k) material that can effectively reduce the signal delays is extensively used in IC chips. However, the low-k material possesses fragile mechanical property and high coefficient of thermal expansion (CTE) compared with silicon chip, which raises the reliability concerns of low-k material integrated into IC chip. The typical reliability failure modes are low-k layer delamination and bump crack under temperature loading during assembly and reliability test. Delamination is occurred in the interface between low-k dielectric layers and underfill material at chip corner. Bump crack is at Under Bump Metallization (UBM) corner. Thus, the adequate underfill material selection becomes very important for both solder bump and low-k chips [1]. This paper mainly characterized FCBGA underfill materials to guide the adequate candidates to prevent failures on low-k chip and solder bump. Firstly, test vehicle was a FCBGA package with heat spreader and was investigated the thermal stress by finite element models. In order to analyze localized low-k structures, sub-modeling technique is used for underfill characterizations. Then, the proper underfill candidates picked from modeling results were experimentally validated by reliability tests. Finally, various low-k FCBGA package structures were also studied with same finite element technique.


1999 ◽  
Vol 563 ◽  
Author(s):  
E. S. Drexler

AbstractThe mismatch between the coefficients of thermal expansion of silicon chips and their organic substrates has been mitigated through the practice of using underfill in flip-chip packages. Yet solder fatigue and package failures still occur. This is particularly true for flip-chips on organic substrates that are thermally cycled between low (−55 °C) and high temperatures (125 °C). In this study, I used electron-beam moir6 to measure displacements and calculate strains in a solderball contained in a flip-chip plastic-ball grid array package. A crossed-line grating with a pitch of 450 nm was used to allow detailed measurements of the local displacements from a cross section of a flip-chip package. Elastic displacements were observed and measured, and the v-field displacements, out of the plane of the chip, were more significant than the shear or u-field, in the plane of the chip, displacements. Larger v-field displacements were measured near the center of the silicon chip than at the edge of the chip.


2006 ◽  
Vol 306-308 ◽  
pp. 1043-1048
Author(s):  
Yi-Ming Jen ◽  
Hsi Hsin Chien ◽  
Tsung-Shu Lin ◽  
Shih Hsiang Huang

This research studied the thermal fatigue life for eutectic solder balls of thermally enhanced flip-chip plastic ball grid array (FC-PBGA) packages with different lid materials under thermal cycling tests. Three FC-PBGA packages with different lid materials, i.e., Al, AlSiC, and Cu, were utilized to examine the lid material effect on solder ball reliability. The cyclic stress/strain behavior for the packages was estimated by using the nonlinear finite element method. The eutectic solder was assumed to be elastic-plastic-creep. The stable stress/strain results obtained from FEM analysis were utilized to predict the thermal fatigue life of solder balls by using the Coffin-Manson prediction model. Simulation results showed that the fatigue life of the FC-PBGA package with a Cu lid was much shorter than FC-PBGA packages with other lid materials. The relatively shorter fatigue life for the FC-PBGA package with a Cu lid was due to the complex constrained behavior caused by the thermal mismatch between the lid, substrate and the printed circuit board. The difference was insignificant in the fatigue lives between the package with an Al lid and the conventional package.


Sign in / Sign up

Export Citation Format

Share Document