Process metrology of cobalt damascene interconnects

Author(s):  
Eugene Shalyt ◽  
Michael Palvov ◽  
Xiaodong Yan ◽  
Danni Lin
1996 ◽  
Vol 427 ◽  
Author(s):  
H. J. Barth

AbstractToday different Al-fill techniques are used for the fill of submicron contacts and vias. The integration aspects of the most promising approaches, Al-reflow, cold/hot Al-planarization and high pressure Al-fill (Forcefill) are compared to the widely used W-plug technique. The filling properties are discussed with respect to future applications in ULSI devices. Special attention is given to the barrier stability in contacts and the influence on patterning. Various electrical data and reliability results are compared to metallizations with W-plugs. The implications of the Al-fill processes on chip design, especially on the size and shape of holes, the pattern density, the possibility of producing stacked contacts/vias and the metal to contact/via overlap are considered also. In an outlook for future developments, e.g. the introduction of low k dielectrics, the inverse metallization architecture with (dual) damascene interconnects and the emerging Cu metallizations, Alfill processes are facing new challenges which will be discussed.


2009 ◽  
Vol 2 (9) ◽  
pp. 096503 ◽  
Author(s):  
Christopher J. Wilson ◽  
Kristof Croes ◽  
Zsolt Tőkei ◽  
Bart Vereecke ◽  
Gerald P. Beyer ◽  
...  

2004 ◽  
Vol 812 ◽  
Author(s):  
Z. -S. Choi ◽  
C. L. Gan ◽  
F. Wei ◽  
C. V. Thompson ◽  
J. H. Lee ◽  
...  

AbstractThe median-times-to-failure (t50's) for straight dual-damascene via-terminated copper interconnect structures, tested under the same conditions, depend on whether the vias connect down to underlaying leads (metal 2, M2, or via-below structures) or connect up to overlaying leads (metal 1, M1, or via-above structures). Experimental results for a variety of line lengths, widths, and numbers of vias show higher t50's for M2 structures than for analogous M1 structures. It has been shown that despite this asymmetry in lifetimes, the electromigration drift velocity is the same for these two types of structures, suggesting that fatal void volumes are different in these two cases. A numerical simulation tool based on the Korhonen model has been developed and used to simulate the conditions for void growth and correlate fatal void sizes with lifetimes. These simulations suggest that the average fatal void size for M2 structures is more than twice the size of that of M1 structures. This result supports an earlier suggestion that preferential nucleation at the Cu/Si3N4 interface in both M1 and M2 structures leads to different fatal void sizes, because larger voids are required to span the line thickness in M2 structures while smaller voids below the base of vias can cause failures in M1 structures. However, it is also found that the fatal void sizes corresponding to the shortest-times-to-failure (STTF's) are similar for M1 and M2, suggesting that the voids that lead to the shortest lifetimes occur at or in the vias in both cases, where a void need only span the via to cause failure. Correlation of lifetimes and critical void volumes provides a useful tool for distinguishing failure mechanisms.


2000 ◽  
Vol 612 ◽  
Author(s):  
Shyama P. Mukherjee ◽  
Joseph A. Levert ◽  
Donald S. Debear

ABSTRACTThe present work describes the process principles of “Spin-Etch Planarization” (SEP), an emerging method of planarization of dual damascene copper interconnects. The process involves a uniform removal of copper and the planarization of surface topography of copper interconnects by dispensing abrasive free etchants to a rotating wafer. The primary process parameters comprise of (a) Physics and chemistry of etchants, and (b) Nature of fluid flow on a spinning wafer. It is evident, that unlike conventional chemical-mechanical planarization, which has a large number of variables due to the presence of pads, normal load, and abrasives, SEP has a smaller number of process parameters and most of them are primary in nature. Based on our preliminary works, we have presented the basic technical parameters that contribute to the process and satisfy the basic requirements of planarization such as (a) Uniformity of removal (b) Removal rate (c) Degree of Planarization (d) Selectivity. The anticipated advantages and some inherent limitations are discussed in the context of process principles. We believe that when fully developed, SEP will be a simple, predictable and controllable process.


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