BGA packaged IC sample preparing for electrical failure analysis

2008 ◽

Author(s):

P. Schwindenhammer ◽

H. Murray ◽

P. Descamps ◽

P. Poirier

Keyword(s):

Laser Ablation ◽

Integrated Circuits ◽

Failure Analysis ◽

Ablation Process ◽

Thermally Induced ◽

Electrical Failure ◽

Electrical Phenomenon ◽

Semiconductor Packages ◽

Complex Semiconductor

Abstract Decapsulation of complex semiconductor packages for failure analysis is enhanced by laser ablation. If lasers are potentially dangerous for Integrated Circuits (IC) surface they also generate a thermal elevation of the package during the ablation process. During measurement of this temperature it was observed another and unexpected electrical phenomenon in the IC induced by laser. It is demonstrated that this new phenomenon is not thermally induced and occurs under certain ablation conditions.

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Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis

ISTFA 2002: Conference Proceedings from the 28th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2002p0771 ◽

2002 ◽

Author(s):

Hui Pan ◽

Thomas Gibson

Keyword(s):

Failure Analysis ◽

Focused Ion Beam ◽

Ion Beam ◽

Electrical Characterization ◽

Charge Pump ◽

Front Side ◽

Pump Failure ◽

Electrical Failure ◽

Optical Proximity Correction ◽

A Charge

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.

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SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

ISTFA 2020: Papers Accepted for the Planned 46th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2020p0322 ◽

2020 ◽

Author(s):

Hyungtae Kim ◽

Geonho Kim ◽

Yunrong Li ◽

Jinyong Jeong ◽

Youngdae Kim

Keyword(s):

Failure Analysis ◽

Technology Development ◽

New Technology ◽

Random Access ◽

Analysis Data ◽

Test Method ◽

Design For Test ◽

Defect Identification ◽

Electrical Failure ◽

Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

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Analysis of Forward Surge Performance of SiC Schottky Diodes

Materials Science Forum ◽

10.4028/www.scientific.net/msf.924.621 ◽

2018 ◽

Vol 924 ◽

pp. 621-624 ◽

Cited By ~ 4

Author(s):

Rahul Radhakrishnan ◽

Nathanael Cueva ◽

Tony Witt ◽

Richard L. Woodin

Keyword(s):

Silicon Carbide ◽

Failure Analysis ◽

Ohmic Contact ◽

Schottky Diodes ◽

Forward Bias ◽

Device Failure ◽

Electrical Failure ◽

The Impact ◽

Surge Current

Silicon Carbide JBS diodes are capable, in forward bias, of carrying surge current of magnitude significantly higher than their rated current, for short periods. In this work, we examine the mechanisms of device failure due to excess surge current by analyzing variation of failure current with device current and voltage ratings, as well as duration of current surge. Physical failure analysis is carried out to correlate to electrical failure signature. We also quantify the impact, on surge current capability, of the resistance of the anode ohmic contact to the p-shielding region.

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Electrical failure analysis in high density DRAMs

Proceedings of IEEE International Workshop on Memory Technology, Design, and Test ◽

10.1109/mtdt.1994.397201 ◽

2002 ◽

Cited By ~ 5

Author(s):

A. Chan ◽

D. Lam ◽

W. Tan ◽

Swee Yong Khim

Keyword(s):

Failure Analysis ◽

High Density ◽

Electrical Failure

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SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

10.31399/asm.cp.istfa2021p0080 ◽

2021 ◽

Author(s):

Hyungtae Kim ◽

Geonho Kim ◽

Yunrong Li ◽

Jinyong Jeong ◽

Youngdae Kim

Keyword(s):

Failure Analysis ◽

Technology Development ◽

New Technology ◽

Random Access ◽

Analysis Data ◽

Test Method ◽

Design For Test ◽

Defect Identification ◽

Electrical Failure ◽

Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

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SRAM Bitcell Defect Identification Methodology Using Electrical Failure Analysis Data

10.31399/asm.cp.istfa2021p0316 ◽

2021 ◽

Author(s):

Hyungtae Kim ◽

Geonho Kim ◽

Yunrong Li ◽

Jinyong Jeong ◽

Youngdae Kim

Keyword(s):

Failure Analysis ◽

Technology Development ◽

New Technology ◽

Random Access ◽

Analysis Data ◽

Test Method ◽

Design For Test ◽

Defect Identification ◽

Electrical Failure ◽

Efficient Test

Abstract Static Random Access Memory (SRAM) has long been used for a new technology development vehicle because it is sensitive to process defects due to its high density and minimum feature size. In addition, failure location can be accurately predicted because of the highly structured architecture. Thus, fast and accurate Failure Analysis (FA) of the SRAM failure is crucial for the success of new technology learning and development. It is often quite time consuming to identify defects through conventional physical failure analysis techniques. In this paper, we present an advanced defect identification methodology for SRAM bitcell failures with fast speed and high accuracy based on the bitcell transistor analog characteristics from special design for test (DFT) features, Direct Bitcell Access (DBA). This technique has the advantage to shorten FA throughput time due to a time efficient test method and an intuitive failure analysis method based on Electrical Failure Analysis (EFA) without destructive analysis. In addition, all the defects in a wafer can be analyzed and improved simultaneously utilizing the proposed defect identification methodology. Some successful case studies are also discussed to demonstrate the efficiency of the proposed defect identification methodology.

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