On-chip protection in precision integrated circuits operating at high voltage and high temperature

Author(s):  
James Zhao ◽  
Javier A. Salcedo ◽  
Jean-Jacques Hajjar
2019 ◽  
Vol 963 ◽  
pp. 832-836 ◽  
Author(s):  
Shuo Ben Hou ◽  
Per Erik Hellström ◽  
Carl Mikael Zetterling ◽  
Mikael Östling

This paper presents our in-house fabricated 4H-SiC n-p-n phototransistors. The wafer mapping of the phototransistor on two wafers shows a mean maximum forward current gain (βFmax) of 100 at 25 °C. The phototransistor with the highest βFmax of 113 has been characterized from room temperature to 500 °C. βFmax drops to 51 at 400 °C and remains the same at 500 °C. The photocurrent gain of the phototransistor is 3.9 at 25 °C and increases to 14 at 500 °C under the 365 nm UV light with the optical power of 0.31 mW. The processing of the phototransistor is same to our 4H-SiC-based bipolar integrated circuits, so it is a promising candidate for 4H-SiC opto-electronics on-chip integration.


2011 ◽  
Vol 679-680 ◽  
pp. 758-761 ◽  
Author(s):  
Luigia Lanni ◽  
Reza Ghandi ◽  
Martin Domeij ◽  
Carl Mikael Zetterling ◽  
Bengt Gunnar Malm ◽  
...  

In this work, a 4H-SiC lateral PNP transistor fabricated in a high voltage NPN technology has been simulated and characterized. The possibility of fabricating a lateral PNP with a current gain larger than 1 has been investigated. Device and circuit level solutions have been performed.


2017 ◽  
Vol 897 ◽  
pp. 669-672 ◽  
Author(s):  
Shinichiro Kuroki ◽  
Tatsuya Kurose ◽  
Hirofumi Nagatsuma ◽  
Seiji Ishikawa ◽  
Tomonori Maeda ◽  
...  

For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200°C. For future SiC large integrated circuits, junction leakage current between n+ regions were also investigated with the comb-shaped test elements.


2008 ◽  
Vol 600-603 ◽  
pp. 1091-1094 ◽  
Author(s):  
Y. Zhang ◽  
Kuang Sheng ◽  
Ming Su ◽  
Jian Hui Zhao ◽  
Petre Alexandrov ◽  
...  

A series of high voltage (HV) and low voltage (LV) lateral JFETs are successfully developed in 4H-SiC based on the vertical channel LJFET (VC-LJFET) device platform. Both room temperature and 300 oC characterizations are presented. The HV JFET shows a specific-on resistance of 12.8 mΩ·cm2 and is capable of conducting current larger than 3 A at room temperature. A threshold voltage drop of about 0.5 V for HV and LV JFETs is observed when temperature varies from room temperature to 300 oC. The measured increase of specific-on resistance with temperature due to a reduction of electron mobility agrees with the numerical prediction. The first demonstration of SiC power integrated circuits (PIC) is also reported, which shows 5 MHz switching at VDS of 200 V and on-state current of 0.4 A.


Author(s):  
N.J. Tighe ◽  
H.M. Flower ◽  
P.R. Swann

A differentially pumped environmental cell has been developed for use in the AEI EM7 million volt microscope. In the initial version the column of gas traversed by the beam was 5.5mm. This permited inclusion of a tilting hot stage in the cell for investigating high temperature gas-specimen reactions. In order to examine specimens in the wet state it was found that a pressure of approximately 400 torr of water saturated helium was needed around the specimen to prevent dehydration. Inelastic scattering by the water resulted in a sharp loss of image quality. Therefore a modified cell with an ‘airgap’ of only 1.5mm has been constructed. The shorter electron path through the gas permits examination of specimens at the necessary pressure of moist helium; the specimen can still be tilted about the side entry rod axis by ±7°C to obtain stereopairs.


2012 ◽  
Vol E95.C (7) ◽  
pp. 1244-1251 ◽  
Author(s):  
Koji TAKEDA ◽  
Tomonari SATO ◽  
Takaaki KAKITSUKA ◽  
Akihiko SHINYA ◽  
Kengo NOZAKI ◽  
...  

Author(s):  
Carl M. Nail

Abstract Dice must often be removed from their packages and reassembled into more suitable packages for them to be tested in automated test equipment (ATE). Removing bare dice from their substrates using conventional methods poses risks for chemical, thermal, and/or mechanical damage. A new removal method is offered using metallography-based and parallel polishing-based techniques to remove the substrate while exposing the die to minimized risk for damage. This method has been tested and found to have a high success rate once the techniques are learned.


1993 ◽  
Vol 320 ◽  
Author(s):  
S. P. Murarka

ABSTRACTSilicides have found application as high conductivity, high temperature, and corrosion resistance materials that form good electrical contacts to silicon and good low resistivity cladding on polysilicon films used as gate metal. Of various silicides investigated in past CoSi2 offers several advantages including lowest resistivity, self-aligned formation, low lattice mismatch with silicon, stability in presence of dopants and on SiO2, Si3N4, or Sioxynitrides, and reliability to process temperatures ≤900°C even when used in thicknesses as thin as 50-60 nm. Thus, CoSi2 has found an application in VLSI and ULSI. In this paper, the properties, formation and processing, reliability, and applicability of CoSi2 will be reviewed. It will be shown that CoSi2 is only silicide that offers properties and reliability for continued use in sub-0.25 pm VLSI and ULSI integrated circuits.


2021 ◽  
Author(s):  
Viktoriia Mishukova ◽  
Nicolas Boulanger ◽  
Artem Iakunkov ◽  
Szymon Sollami Delekta ◽  
Xiaodong Zhuang ◽  
...  

Many industry applications require electronic circuits and systems to operate at high temperature over 150 oC. Although planar microsupercapacitors (MSCs) have great potential for miniaturized on-chip integrated energy storage components,...


Sign in / Sign up

Export Citation Format

Share Document