A dual edge-triggered phase-frequency detector architecture [frequency synthesizer applications]

2003 ◽  
Author(s):  
S.I. Ahmed ◽  
R.D. Mason
Keyword(s):  
Frequency Synthesizer ◽  
Phase Frequency Detector ◽  
Frequency Detector

scholarly journals Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology

2021 ◽  
Vol 23 (11) ◽  
pp. 184-197
Author(s):  
Pawan Srivastava ◽  
◽  
Dr. Ram Chandra Singh Chauhan ◽  
Keyword(s):  
Frequency Synthesizer ◽  
Supply Voltage ◽  
Process Variations ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Monte Carlo Analysis ◽  
Voltage Controlled Oscillator ◽  
Phase Frequency Detector ◽  
Power Efficient ◽  
Frequency Detector

A novel phase frequency detector is designed which is made up of 16 transistors whereas conventional is of 48 transistors. This paper also presented the design of charge pump circuit and current starved VCO (CSVCO). These are the critical blocks that are widely used for applications like clock and data recovery circuit, PLL, frequency synthesizer. The proposed PFD eliminates the reset circuit using pass transistor logic and operates effectively at higher frequencies. The circuits are designed using Cadence Virtuoso v6.1 in 45nm CMOS technology having supply voltage 1V. It was found that the power consumption of PFD is 138.2 nW which is significantly lesser than other designs. CSVCO also analysed at operating frequency of 10 MHz to give output oscillation frequency of 1.119 GHz with power dissipation of 18.91 μW. Corner analysis done for both the PFD and CSVCO for various process variations. Monte Carlo analysis also done for the proposed PFD and presented CSVCO to test the circuit reliableness.

scholarly journals An integer-N frequency synthesizer for medical implantable devices

2021 ◽  
Author(s):  
Nima Haghighi
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Frequency Synthesizer ◽  
Wide Frequency Range ◽  
Implantable Devices ◽  
Total Power ◽  
Frequency Range ◽  
Phase Frequency Detector ◽  
Frequency Detector ◽  
Low Phase Noise

This thesis proposes an Integer-N frequency synthesizer in TSMC 0.18µm technology. The design is aimed for MICS (Medical Implantable Communication Services) devices operating at 402-406 MHz. A low phase noise, wide frequency range Quadrature Voltage Controlled Oscillator (QVCO) has been designed and simulated. The simulated phase noise @ 160 KHz offset is -100.3 dBc/Hz with the power consumption of 0.9 mW. This design addresses the small size, low phase noise and low power requirements for the Implantable devices. A wide frequency range Source Coupled Logic (SCL)32/33 prescaler divider has been designed. The program counter and Swallow counter have been implemented in Verilog-A which allow a division ratio of 2690 from the output of the QVCO. A phase frequency detector based on a modified TSPC D-Flip Flop is designed, which leads to a faster response time. The phase frequency detector, the charge pump, and the loop filter would consume 0.5 mW power. The total power consumption of the synthesizer is at 4.6 mW with 2% steady state settlement time of 160 μs.

A Novel Design of high performance low power phase frequency Detector for CMOS PLL frequency Synthesizer

2019 ◽  
Vol 09 ◽  
Author(s):  
Monika Bhardwaj ◽  
Sujata Pandey ◽  
Neeta Pandey
Keyword(s):  
Low Power ◽  
Power Supply ◽  
High Performance ◽  
Frequency Synthesizer ◽  
Operating Frequency ◽  
Feedback Signal ◽  
Input Frequency ◽  
Phase Frequency Detector ◽  
Pll Frequency Synthesizer ◽  
Frequency Detector

Aims: A high performance low power phase frequency detector is designed and simulated. The various different parameters of the circuit are obtained through various type of simulations. We worked mainly upon the power dissipation, power supply, input frequency range and its area. The proposed PFD will have the locking capability i.e. to lock at the edges either on the rising or falling edge w.r.t the reference and the feedback signal. The proposed design will have the very high performance and ultra-low phase noise. It has the added advantage of low cost and the compact size. Objective: The primary objective is to design a low power phase frequency detector for CMOS PLL Frequency Synthesizer using lows power technique. Method: The pass transistor logic is used in the circuit to eliminate the reset path. By this change of the path the operating frequency and operating speed both are increased in the proposed design. The input Frequency can be taken up to 5 gigahertz. The power supply is taken to be 1 V. The proposed PFD design will have a less number of transistors and also a low consumption of power. The output pulses of the PFD at phase difference of 0, 0,п/2, п, 3п/2, 2п will have its average voltage as 0, VDD and VDD/2. The proposed phase detector will perfectly detect the phase difference between two signals so that the harmonics problem can be minimized. Result: The proposed design is having its operating frequency as 5GHz over the conventional one which has its frequency as 800MHz. Power dissipation in the proposed design is reduced due to less number of transistors used as compared with the conventional one. The operating region has become much wider for proposed design as it is having operating frequency much higher than that of the conventional one. Conclusion: The proposed PFD will increase the locking capability on the both rise and fall edge w.r.t. the reference and the feedback signal. The input Frequency can be taken up to 5 gigahertz. The power supply is taken to be 1 V. The proposed PFD circuit will have a less number of transistors and also a low consumption of power 7.14 mW.

scholarly journals A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS

Electronics ◽  
2020 ◽  
Vol 9 (9) ◽  
pp. 1502
Author(s):  
Waseem Abbas ◽  
Zubair Mehmood ◽  
Munkyo Seo
Keyword(s):  
Frequency Synthesizer ◽  
Dead Zone ◽  
Phase Locked Loop ◽  
Voltage Controlled Oscillator ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Chip Area ◽  
V Band ◽  
Locking Range ◽  
Frequency Detector

A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.

scholarly journals An integer-N frequency synthesizer for medical implantable devices

2021 ◽  
Author(s):  
Nima Haghighi
Keyword(s):  
Power Consumption ◽  
Phase Noise ◽  
Frequency Synthesizer ◽  
Wide Frequency Range ◽  
Implantable Devices ◽  
Total Power ◽  
Frequency Range ◽  
Phase Frequency Detector ◽  
Frequency Detector ◽  
Low Phase Noise

This thesis proposes an Integer-N frequency synthesizer in TSMC 0.18µm technology. The design is aimed for MICS (Medical Implantable Communication Services) devices operating at 402-406 MHz. A low phase noise, wide frequency range Quadrature Voltage Controlled Oscillator (QVCO) has been designed and simulated. The simulated phase noise @ 160 KHz offset is -100.3 dBc/Hz with the power consumption of 0.9 mW. This design addresses the small size, low phase noise and low power requirements for the Implantable devices. A wide frequency range Source Coupled Logic (SCL)32/33 prescaler divider has been designed. The program counter and Swallow counter have been implemented in Verilog-A which allow a division ratio of 2690 from the output of the QVCO. A phase frequency detector based on a modified TSPC D-Flip Flop is designed, which leads to a faster response time. The phase frequency detector, the charge pump, and the loop filter would consume 0.5 mW power. The total power consumption of the synthesizer is at 4.6 mW with 2% steady state settlement time of 160 μs.

Effect of Scaling on Phase Frequency Detector

2016 ◽  
Vol 7 (1) ◽  
pp. 20
Author(s):  
GULIHAR LATIKA ◽  
KRISHAN BAL ◽  
◽  
Keyword(s):  
Phase Frequency Detector ◽  
Frequency Detector

МАКРОМОДЕЛИРОВАНИЕ СХЕМЫ ФАПЧ С ИСПОЛЬЗОВАНИЕМ ПОЛНОЙ ПРИНЦИПИАЛЬНОЙ СХЕМЫ ФАЗОВОГО ДЕТЕКТОРА

2020 ◽  
Vol 96 (3s) ◽  
pp. 295-299
Author(s):  
М.М. Гурарий ◽  
М.М. Жаров ◽  
Л.П. Ионов ◽  
И.И. Мухин ◽  
С.Г. Русаков ◽  
...  
Keyword(s):  
Electric Circuit ◽  
Schematic Diagram ◽  
Equivalent Electric Circuit ◽  
Phase Frequency Detector ◽  
Frequency Detector ◽  
A Current

В работе рассмотрены проблемы анализа схем ФАПЧ с учетом наличия неидеальностей в схеме частотно-фазового детектора с токовым ключом. Для снижения затрат на моделирование предложено использовать эквивалентную электрическую схему, содержащую полную принципиальную схему ЧФД и схемные эквиваленты макромоделей остальных блоков ФАПЧ. The paper considers the problems of analyzing the PLL circuit taking into account the presence of nonidealities in the phase-frequency detector with a current key. To reduce the simulation efforts, it has been proposed to apply an equivalent electric circuit containing the complete schematic diagram of the PFD and circuit equivalents of the macromodels of other PLL blocks.

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