A V-Band Phase-Locked Loop with a Novel Phase-Frequency Detector in 65 nm CMOS

A 65–67 GHz phase-locked loop (PLL) with a novel low power phase-frequency detector (PFD) in 65 nm LP CMOS is presented. The PLL consists of a V-band voltage-controlled oscillator (VCO), a divide-by-two injection-locked frequency divider (ILFD), and a current-mode logic (CML) divider chain. A charge pump (CP) and a 2nd-order loop filter are used with PFD for VCO tuning. The PFD is implemented with 16 transistors with dead-zone-free capability. The measured locking range of the PLL is from 65.15 to 67.4 GHz, with −11.5 dBm measured output power at 66.05 GHz while consuming 88 mW. The measured phase noise at 1 MHz offset is −84.43 dBc/Hz. The chip area of the PLL is 0.84 mm2 including probing pads. The proposed PLL can be utilized as a frequency synthesizer for carrier signal generation in IEEE 802.11ad standard high data rate transceiver circuits.

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Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

Indonesian Journal of Electrical Engineering and Computer Science ◽

10.11591/ijeecs.v4.i2.pp397-405 ◽

2016 ◽

Vol 4 (2) ◽

pp. 397

Author(s):

P.N. Metange ◽

K. B. Khanchandani

Keyword(s):

Leakage Current ◽

High Performance ◽

Charge Pump ◽

Phase Locked Loop ◽

Loop Filter ◽

Phase Frequency Detector ◽

Analysis And Design ◽

Wireless Applications ◽

5 Ghz ◽

Frequency Detector

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications. The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

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A Ku-Band Fractional-N Frequency Synthesizer with Adaptive Loop Bandwidth Control

Electronics ◽

10.3390/electronics10020109 ◽

2021 ◽

Vol 10 (2) ◽

pp. 109

Author(s):

Youming Zhang ◽

Xusheng Tang ◽

Zhennan Wei ◽

Kaiye Bao ◽

Nan Jiang

Keyword(s):

Phase Noise ◽

Frequency Synthesizer ◽

Frequency Tuning ◽

Cmos Technology ◽

Voltage Controlled Oscillator ◽

Loop Filter ◽

Chip Area ◽

Loop Bandwidth ◽

Bandwidth Control ◽

Ku Band

This paper presents a Ku-band fractional-N frequency synthesizer with adaptive loop bandwidth control (ALBC) to speed up the lock settling process and meanwhile ensure better phase noise and spur performance. The theoretical analysis and circuits implementation are discussed in detail. Other key modules of the frequency synthesizer such as broadband voltage-controlled oscillator (VCO) with auto frequency calibration (AFC) and programable frequency divider/charge pump/loop filter are designed for integrity and flexible configuration. The proposed frequency synthesizer is fabricated in 0.13 μm CMOS technology occupying 1.14 × 1.18 mm2 area including ESD/IOs and pads, and the area of the ALBC is only 55 × 76 μm2. The out frequency can cover from 11.37 GHz to 14.8 GHz with a frequency tuning range (FTR) of 26.2%. The phase noise is −112.5 dBc/Hz @ 1 MHz and −122.4 dBc/Hz @ 3 MHz at 13 GHz carrier frequency. Thanks to the proposed ALBC, the lock-time can be shortened by about 30% from about 36 μs to 24 μs. The chip area and power consumption of the proposed ALBC technology are slight, but the beneficial effect is significant.

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Design of Power Efficient Phase Frequency Detector and Voltage Controlled Oscillator for PLL Applications in 45 nm CMOS Technology

Journal of University of Shanghai for Science and Technology ◽

10.51201/jusst/21/10879 ◽

2021 ◽

Vol 23 (11) ◽

pp. 184-197

Author(s):

Pawan Srivastava ◽

◽

Dr. Ram Chandra Singh Chauhan ◽

Keyword(s):

Frequency Synthesizer ◽

Supply Voltage ◽

Process Variations ◽

Clock And Data Recovery ◽

Cmos Technology ◽

Monte Carlo Analysis ◽

Voltage Controlled Oscillator ◽

Phase Frequency Detector ◽

Power Efficient ◽

Frequency Detector

A novel phase frequency detector is designed which is made up of 16 transistors whereas conventional is of 48 transistors. This paper also presented the design of charge pump circuit and current starved VCO (CSVCO). These are the critical blocks that are widely used for applications like clock and data recovery circuit, PLL, frequency synthesizer. The proposed PFD eliminates the reset circuit using pass transistor logic and operates effectively at higher frequencies. The circuits are designed using Cadence Virtuoso v6.1 in 45nm CMOS technology having supply voltage 1V. It was found that the power consumption of PFD is 138.2 nW which is significantly lesser than other designs. CSVCO also analysed at operating frequency of 10 MHz to give output oscillation frequency of 1.119 GHz with power dissipation of 18.91 μW. Corner analysis done for both the PFD and CSVCO for various process variations. Monte Carlo analysis also done for the proposed PFD and presented CSVCO to test the circuit reliableness.

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Design and Implementation of High Frequency and Low-Power Phase-locked Loop

U Porto Journal of Engineering ◽

10.24840/2183-6493_007.004_0006 ◽

2021 ◽

Vol 7 (4) ◽

pp. 70-86

Author(s):

Premananda B. S. ◽

Dhanush T. N. ◽

Vaishnavi S. Parashar ◽

D. Aneesh Bharadwaj

Keyword(s):

Power Consumption ◽

High Frequency ◽

Supply Voltage ◽

Phase Locked Loop ◽

Voltage Controlled Oscillator ◽

Switching Rate ◽

Loop Filter ◽

Capture Range ◽

Frequency Detector ◽

Reduced Power Consumption

Phase-locked loop (PLL) operates at a high frequency and due to the increased switching rate of the circuits, the power consumption is high. Designing a PLL which consumes less power without compromising the frequency of operation is essential. The sub-components of PLL such as the phase frequency detector, charge pump, loop filter, voltage-controlled oscillator, and the frequency divider have to be designed for reduced power consumption. The proposed PLL along with its sub-components have been designed using the CMOS 180nm technology library in the Cadence Virtuoso and simulated using Cadence Spectre with a supply voltage of 1.8V resulting in a 20% reduction in power with a higher frequency of operation compared to the reference PLL architecture. The capture range and lock range of the proposed PLL are 2.09 to 2.14 GHz and 1 to 3.5GHz, respectively. The designed PLL consumes less power and operates at a higher frequency.

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A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP

Journal of Circuits System and Computers ◽

10.1142/s0218126605002738 ◽

2005 ◽

Vol 14 (05) ◽

pp. 997-1006 ◽

Cited By ~ 2

Author(s):

ROBERT C. CHANG ◽

LUNG-CHIH KUO ◽

HOU-MING CHEN

Keyword(s):

Low Power ◽

Low Voltage ◽

Supply Voltage ◽

Charge Pump ◽

Phase Locked Loop ◽

Loop Filter ◽

Phase Frequency Detector ◽

Low Power Cmos ◽

Charge Pump Circuit ◽

Frequency Detector

A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.

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Design and Implementation of Charge Pump Phase-Locked Loop Frequency Source Based on GaAs pHEMT Process

Sensors ◽

10.3390/s22020504 ◽

2022 ◽

Vol 22 (2) ◽

pp. 504

Author(s):

Ranran Zhao ◽

Yuming Zhang ◽

Hongliang Lv ◽

Yue Wu

Keyword(s):

Maximum Output Power ◽

Charge Pump ◽

Phase Locked Loop ◽

Low Noise ◽

Signal Frequency ◽

Maximum Output ◽

Voltage Controlled Oscillator ◽

Chip Area ◽

Frequency Source ◽

A Charge

This paper realized a charge pump phase locked loop (CPPLL) frequency source circuit based on 0.15 μm Win GaAs pHEMT process. In this paper, an improved fully differential edge-triggered frequency discriminator (PFD) and an improved differential structure charge pump (CP) are proposed respectively. In addition, a low noise voltage-controlled oscillator (VCO) and a static 64:1 frequency divider is realized. Finally, the phase locked loop (PLL) is realized by cascading each module. Measurement results show that the output signal frequency of the proposed CPPLL is 3.584 GHz–4.021 GHz, the phase noise at the frequency offset of 1 MHz is −117.82 dBc/Hz, and the maximum output power is 4.34 dBm. The chip area is 2701 μm × 3381 μm, and the power consumption is 181 mw.

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