Low Quiescent Current, Capacitor-Less LDO with Adaptively Biased Power Transistors and Load Aware Feedback Resistance

Author(s):  
Battu Balaji Yadav ◽  
Kelam Mounika ◽  
Koushik De ◽  
Zia Abbas
2014 ◽  
Vol 631-632 ◽  
pp. 322-326
Author(s):  
Shang Sheng Chi ◽  
Wei Hu ◽  
Yu Sen Xu ◽  
Ming Hui Fan

This paper presents a bandgap reference and an output-capacitorless LDO regulator with adaptive power transistors. The bandgap reference consists of a current reference circuit, a bipolar transistor and proportional-to-absolute-temperature (PTAT) voltage generators. The proposed LDO improves load transient and light load efficiency by permitting the regulator to transform itself between 2-stage and 3-stage topologies, depending on the load current condition. Cadence simulation with SMIC 0.18 μm process shows that the bandgap reference generates a reference voltage 569 mV and the quiescent current is only 0.23 μA, the proposed LDO generates an output voltage 1 V, the quiescent current is 0.88 μA (including bandgap reference) at no-load condition, the undershoot /overshoot voltage is 187 mV/152 mV and the settling time is 5 μs as load current suddenly changes from 0 to 100 mA, or vice versa.


Materials ◽  
2021 ◽  
Vol 14 (9) ◽  
pp. 2316
Author(s):  
Kalparupa Mukherjee ◽  
Carlo De Santi ◽  
Matteo Borga ◽  
Karen Geens ◽  
Shuzhen You ◽  
...  

The vertical Gallium Nitride-on-Silicon (GaN-on-Si) trench metal-oxide-semiconductor field effect transistor (MOSFET) is a promising architecture for the development of efficient GaN-based power transistors on foreign substrates for power conversion applications. This work presents an overview of recent case studies, to discuss the most relevant challenges related to the development of reliable vertical GaN-on-Si trench MOSFETs. The focus lies on strategies to identify and tackle the most relevant reliability issues. First, we describe leakage and doping considerations, which must be considered to design vertical GaN-on-Si stacks with high breakdown voltage. Next, we describe gate design techniques to improve breakdown performance, through variation of dielectric composition coupled with optimization of the trench structure. Finally, we describe how to identify and compare trapping effects with the help of pulsed techniques, combined with light-assisted de-trapping analyses, in order to assess the dynamic performance of the devices.


2021 ◽  
Vol 11 (3) ◽  
pp. 31
Author(s):  
Anindita Paul ◽  
Mario Renteria-Pinon ◽  
Jaime Ramirez-Angulo ◽  
Ricardo Bolaños-Pérez ◽  
Héctor Vázquez-Leal ◽  
...  

An approach to implement single-ended power-efficient static class-AB Miller op-amps with symmetrical and significantly enhanced slew-rate and accurately controlled output quiescent current is introduced. The proposed op-amp can drive a wide range of resistive and capacitive loads. The output positive and negative currents can be much higher than the total op-amp quiescent current. The enhanced performance is achieved by utilizing a simple low-power auxiliary amplifier with resistive local common-mode feedback that increases the quiescent power dissipation by less than 10%. The proposed class AB op-amp is characterized by significantly enhanced large-signal dynamic, static current efficiency, and small-signal figures of merits. The dynamic current efficiency is 15.6 higher, the static current efficiency is 8.9 times higher, and the small-signal figure of merit is 2.3 times higher than the conventional class-A op-amp. A global figure of merit that determines an op-amp’s ultimate speed is 6.33 times higher than the conventional class A op-amp.


Physica B+C ◽  
1985 ◽  
Vol 129 (1-3) ◽  
pp. 337-341
Author(s):  
Wolf-Dieter Nowak ◽  
Heinrich Schlangenotto

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