Effects of device variations on the EMI potential of high speed digital integrated circuits

2002 ◽  
Author(s):  
J.T. DiBene ◽  
J.L. Knighten
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Digital Integrated Circuits

HIGH SPEED DIGITAL CIRCUIT TECHNOLOGY

1995 ◽  
Vol 06 (01) ◽  
pp. 163-210 ◽  
Author(s):  
STEPHEN I. LONG
Keyword(s):  
Integrated Circuits ◽  
Low Power ◽  
Material Properties ◽  
High Speed ◽  
Digital Circuit ◽  
Bipolar Transistor ◽  
Clock Frequency ◽  
Digital Integrated Circuits ◽  
Heterojunction Devices ◽  
Circuit Technology

The performance of high speed digital integrated circuits, defined here as those requiring operation at high clock frequency, is generally more sensitive to material properties and process techniques than ICs used at lower frequencies. Obtaining high speed and low power concurrently is especially challenging. Circuit architectures must be selected for the device and application appropriately. This paper presents simple models for high speed digital IC performance and applies these to the FET and bipolar transistor. Heterojunction devices are compared with those using single or binary materials. Circuits for high speed SSI and low power VLSI applications are described, and their performance is surveyed.

scholarly journals Optimal Physical Implementation of Radiation Tolerant High-Speed Digital Integrated Circuits in Deep-Submicron Technologies

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 432 ◽  
Author(s):  
Jeffrey Prinzie ◽  
Karel Appels ◽  
Szymon Kulis
Keyword(s):  
Integrated Circuits ◽  
High Speed ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Deep Submicron ◽  
Oxide Semiconductor ◽  
Digital Integrated Circuits ◽  
Physical Implementation ◽  
Radiation Hard ◽  
Radiation Tolerant

This paper presents a novel scalable physical implementation method for high-speed Triple Modular Redundant (TMR) digital integrated circuits in radiation-hard designs. The implementation uses a distributed placement strategy compared to a commonly used bulk 3-bank constraining method. TMR netlist information is used to optimally constrain the placement of both sequential cells and combinational cells. This approach significantly reduces routing complexity, net lengths and dynamic power consumption with more than 60% and 20% respectively. The technique was simulated in a 65 nm Complementary Metal-Oxide Semiconductor (CMOS) technology.

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