Characterization of gate oxide degradation mechanisms in trench-gated power MOSFETs using the charge-pumping technique

Abstract In this work, investigation on the degradation behavior of the 1.2-kV/52-A silicon carbide (SiC) power MOSFETs subjected to repetitive slow power cycling stress have been performed. Electric characteristics have been characterized periodically over the stress and the respective degradation mechanisms also have been analysed. A comprehensive degradation analysis is further conducted after the aging test by virtue of the X-ray inspection system, Scanning Acoustic Microscope (SAM), Scanning Electron Microscope (SEM) and emission microscope (EMMI), etc. Experimental results reveal that both the degradation of gate oxide on chip-level and the degradation of the bond wire and solder layer on package-level have emerged over the cyclic stress. Specifically, growths of threshold voltage (Vth) and gate leakage current (Igss) are thought to be relevant with the degradation of gate oxide by SiC/SiO2 interface states trapping/de-trapping electron on chip-level, while the appearances of the fatigue of bond wire and the delamination of solder layer imply the degradation on package-level. This work may provide some practical guidelines for the assessments towards the reliability of SiC power MOSFETs in power conversion system.

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Physical Failure Analysis Techniques for Front-End-of-Line Defect Analysis

ISTFA 2016: Conference Proceedings from the 42nd International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2016p0182 ◽

2016 ◽

Author(s):

Dirk Doyle ◽

Lawrence Benedict ◽

Fritz Christian Awitan

Keyword(s):

Cross Section ◽

Focused Ion Beam ◽

Ion Beam ◽

Gate Oxide ◽

Top Down ◽

New Techniques ◽

First Case ◽

Transmission Electron ◽

Scanning Transmission

Abstract Novel techniques to expose substrate-level defects are presented in this paper. New techniques such as inter-layer dielectric (ILD) thinning, high keV imaging, and XeF2 poly etch overflow are introduced. We describe these techniques as applied to two different defects types at FEOL. In the first case, by using ILD thinning and high keV imaging, coupled with focused ion beam (FIB) cross section and scanning transmission electron microscopy (STEM,) we were able to judge where to sample for TEM from a top down perspective while simultaneously providing the top down images giving both perspectives on the same sample. In the second case we show retention of the poly Si short after removal of CoSi2 formation on poly. Removal of the CoSi2 exposes the poly Si such that we can utilize XeF2 to remove poly without damaging gate oxide to reveal pinhole defects in the gate oxide. Overall, using these techniques have led to 1) increased chances of successfully finding the defects, 2) better characterization of the defects by having a planar view perspective and 3) reduced time in localizing defects compared to performing cross section alone.

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