Impact of Read Operation on the Performance of HfO2-Based Ferroelectric FETs

2020 ◽  
Vol 41 (9) ◽  
pp. 1420-1423
Author(s):  
Halid Mulaosmanovic ◽  
Stefan Dunkel ◽  
Johannes Muller ◽  
Martin Trentzsch ◽  
Sven Beyer ◽  
...  
Keyword(s):  
Author(s):  
Jonathan Shaw ◽  
Christopher McMahon ◽  
Yin Shyang Ng ◽  
Félix Beaudoi

Abstract This paper presents the use of Dynamic Laser Stimulation (DLS) and Time-Resolved DLS (TR-DLS) to provide fail site localization and complementary information on a failed embedded memory IC. In this study, an embedded dual port RAM within a 90nm IC that failed one of the Memory Built-In Self Tests (MBISTs) was investigated. This technique rapidly localized the failing area within the memory read/write circuitry. The TR-DLS provided maps for each operation of the MBIST pattern. With this information, the failure was clearly identified as a read operation failure. The TR-DLS technique also provided much refined site signature (down to just one net) within the sense amp of the Port B of the dual port RAM. This information provided very specific indication on how to improve the operation of that particular sense amp circuitry within the dual port RAM Memory.


2022 ◽  
Vol 21 (1) ◽  
pp. 1-24
Author(s):  
Sheel Sindhu Manohar ◽  
Sparsh Mittal ◽  
Hemangee K. Kapoor

In the deep sub-micron region, “spin-transfer torque RAM” (STT-RAM ) suffers from “read-disturbance error” (RDE) , whereby a read operation disturbs the stored data. Mitigation of RDE requires restore operations, which imposes latency and energy penalties. Hence, RDE presents a crucial threat to the scaling of STT-RAM. In this paper, we offer three techniques to reduce the restore overhead. First, we avoid the restore operations for those reads, where the block will get updated at a higher level cache in the near future. Second, we identify read-intensive blocks using a lightweight mechanism and then migrate these blocks to a small SRAM buffer. On a future read to these blocks, the restore operation is avoided. Third, for data blocks having zero value, a write operation is avoided, and only a flag is set. Based on this flag, both read and restore operations to this block are avoided. We combine these three techniques to design our final policy, named CORIDOR. Compared to a baseline policy, which performs restore operation after each read, CORIDOR achieves a 31.6% reduction in total energy and brings the relative CPI (cycle-per-instruction) to 0.64×. By contrast, an ideal RDE-free STT-RAM saves 42.7% energy and brings the relative CPI to 0.62×. Thus, our CORIDOR policy achieves nearly the same performance as an ideal RDE-free STT-RAM cache. Also, it reaches three-fourths of the energy-saving achieved by the ideal RDE-free cache. We also compare CORIDOR with four previous techniques and show that CORIDOR provides higher restore energy savings than these techniques.


Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 224 ◽  
Author(s):  
Zhensen Tang ◽  
Yao Wang ◽  
Yaqing Chi ◽  
Liang Fang

In this paper, the dependence of sensing currents on various device parameters is comprehensively studied by simulating the complete crossbar array rather than its equivalent analytical model. The worst-case scenario for read operation is strictly analyzed and defined in terms of selected location and data pattern, respectively, based on the effect of parasitic sneak paths and interconnection resistance. It is shown that the worst-case data pattern depends on the trade-off between the shunting effect of the parasitic sneak paths and the current injection effect of the parasitic sneak leakage, thus requiring specific analysis in practical simulations. In dealing with that, we propose a concept of the threshold array size incorporating the trade-off to define the parameter-dependent worst-case data pattern. This figure-of-merit provides guidelines for the worst-case scenario analysis of the crossbar array read operations.


2008 ◽  
Vol E91-C (5) ◽  
pp. 731-735 ◽  
Author(s):  
S. CHO ◽  
I. H. PARK ◽  
J. H. LEE ◽  
J.-G. YUN ◽  
D.-H. KIM ◽  
...  

Integration ◽  
2016 ◽  
Vol 54 ◽  
pp. 56-64 ◽  
Author(s):  
Yansong Gao ◽  
Omid Kavehei ◽  
Said F. Al-Sarawi ◽  
Damith C. Ranasinghe ◽  
Derek Abbott

2007 ◽  
Vol 42 (1) ◽  
pp. 210-218 ◽  
Author(s):  
Sangbeom Kang ◽  
Woo Yeong Cho ◽  
Beak-Hyung Cho ◽  
Kwang-Jin Lee ◽  
Chang-Soo Lee ◽  
...  

A dual port memory in QCA are a study of data in different ports, but the data conflicts are very difficult to identify. Dual port memory is mainly focused on the data priority. It can be generated from the design of the control logic block. Priority bit are used, where both ports access the same memory location. Dual port memory functionality can be identified with a priority bit. When the port having the same memory location, only the port having the high priority is selected and other port are discarded. But when the read operation are requested to both the ports at same locations, having no conflicts and both the ports are requested to perform read operations. Data conflicts on the SRAM cell can be overcome by discarding the lower priority completely. Priorities are defined in terms of the area and delay. The idea behind this work is to minimize the area and delay in the dual port memory and proposed a multilayer Cross-Over design to provide an efficiency to the dual port memory and simulation result of design are shown in QCA Designer Tool-2.0.


2020 ◽  
Vol 54 ◽  
pp. 3
Author(s):  
Benedek Nagy ◽  
Friedrich Otto

Linear automata with translucent letters are studied. These are finite-state acceptors that have two heads that read the input from opposite sides and for which a set of translucent letters is associated with each state. Thus, head 1, which proceeds from left to right, does not necessarily read the first letter of the current tape content, but it skips a prefix that consists of translucent letters only and reads the first letter after that prefix. Analogously, head 2, which proceeds from right to left, does not necessarily read the last letter, but it skips a suffix that consists of translucent letters only and reads the last letter before that. After such a read operation, the head always returns to its corresponding end of the tape. These linear automata with translucent letters are a generalization of the finite-state acceptors with translucent letters that were studied by the authors in B. Nagy and F. Otto [Finite-state acceptors with translucent letters. In BILC 2011, Proc., edited by G. Bel-Enguix, V. Dahl, and A.O. De La Pente, SciTePress, Portugal (2011) 3-13.] It is shown that these linear automata are strictly more expressive than the model with a single head, but that they still only accept languages that have a semi-linear Parikh image. On the other hand, we obtain a characterization for the class of linear context-free trace languages in terms of a specific class of linear automata with translucent letters.


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