A ${Ka}$ -Band Dual-Mode Power Amplifier in 65-nm CMOS Technology

2018 ◽  
Vol 28 (8) ◽  
pp. 708-710 ◽  
Author(s):  
Shuo-Hsuan Chang ◽  
Chun-Nien Chen ◽  
Huei Wang
Keyword(s):  
Power Amplifier ◽  
Cmos Technology ◽  
Dual Mode

Class-F Power Amplifier with Dual-Mode Filtering Response

2021 ◽  
Author(s):  
Liheng Zhou ◽  
Xinyu Zhou ◽  
Zhen Xing Yang ◽  
Wing Shina Chan
Keyword(s):  
Power Amplifier ◽  
Dual Mode ◽  
Class F

An Efficient Mixed-Signal 2.4-GHz Polar Power Amplifier in 65-nm CMOS Technology

2011 ◽  
Vol 46 (8) ◽  
pp. 1796-1809 ◽  
Author(s):  
Debopriyo Chowdhury ◽  
Lu Ye ◽  
Elad Alon ◽  
Ali M. Niknejad
Keyword(s):  
Power Amplifier ◽  
Cmos Technology ◽  
Mixed Signal

A GaAs power amplifier for 3.3 V CDMA/AMPS dual-mode cellular phones

1995 ◽  
Vol 43 (12) ◽  
pp. 2839-2844 ◽  
Author(s):  
Sung-Jae Maeng ◽  
Soung-Soon Chun ◽  
Jong-Lam Lee ◽  
Chang-Seok Lee ◽  
Kwang-Jun Youn ◽  
...  
Keyword(s):  
Power Amplifier ◽  
Cellular Phones ◽  
Dual Mode

scholarly journals A –5 dBm 400MHz OOK Transmitter for Wireless Medical Application

2014 ◽  
Vol 60 (2) ◽  
pp. 193-198
Author(s):  
M. Yousefi ◽  
D. Koozehkanani ◽  
H. Jangi ◽  
N. Nasirzadeh ◽  
J. Sobhi
Keyword(s):  
Energy Consumption ◽  
Power Amplifier ◽  
High Efficiency ◽  
Medical Application ◽  
Cmos Technology ◽  
High Energy ◽  
Data Rate ◽  
High Data Rate ◽  
Low Power Consumption ◽  
High Data

Abstract A 400 MHz high efficiency transmitter for wireless medical application is presented in this paper. Transmitter architecture with high-energy efficiencies is proposed to achieve high data rate with low power consumption. In the on-off keying transmitters, the oscillator and power amplifier are turned off when the transmitter sends 0 data. The proposed class-e power amplifier has high efficiency for low level output power. The proposed on-off keying transmitter consumes 1.52 mw at -5 dBm output by 40 Mbps data rate and energy consumption 38 pJ/bit. The proposed transmitter has been designed in 0.18μm CMOS technology.

A 31 GHz body-biased configurable power amplifier in 28 nm FD-SOI CMOS for 5 G applications

2020 ◽  
pp. 1-18
Author(s):  
Florent Torres ◽  
Eric Kerhervé ◽  
Andreia Cathelin ◽  
Magali De Matos
Keyword(s):  
Power Amplifier ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Silicon On Insulator ◽  
Oxide Semiconductor ◽  
Fully Depleted ◽  
Technology Roadmap ◽  
Wide Range ◽  
28 Nm ◽  
Soi Cmos

Abstract This paper presents a 31 GHz integrated power amplifier (PA) in 28 nm Fully Depleted Silicon-On-Insulator Complementary Metal Oxide Semiconductor (FD-SOI CMOS) technology and targeting SoC implementation for 5 G applications. Fine-grain wide range power control with more than 10 dB tuning range is enabled by body biasing feature while the design improves voltage standing wave ratio (VSWR) robustness, stability and reverse isolation by using optimized 90° hybrid couplers and capacitive neutralization on both stages. Maximum power gain of 32.6 dB, PAEmax of 25.5% and Psat of 17.9 dBm are measured while robustness to industrial temperature range and process spread is demonstrated. Temperature-induced performance variation compensation, as well as amplitude-to-phase modulation (AM-PM) optimization regarding output power back-off, are achieved through body-bias node. This PA exhibits an International Technology Roadmap for Semiconductors figure of merit (ITRS FOM) of 26 925, the highest reported around 30 GHz to authors' knowledge.

scholarly journals Design of a V Band Power Amplifier Using 65 nm CMOS Technology

2013 ◽  
Vol 24 (4) ◽  
pp. 403-409
Author(s):  
Sungah Lee ◽  
Chenglin Cui ◽  
Seong-Kyun Kim ◽  
Byung-Sung Kim
Keyword(s):  
Power Amplifier ◽  
Cmos Technology ◽  
V Band ◽  
Band Power

scholarly journals A 2.5-GHz 1-V High Efficiency CMOS Power Amplifier IC with a Dual-Switching Transistor and Third Harmonic Tuning Technique

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 69 ◽  
Author(s):  
Taufiq Alif Kurniawan ◽  
Toshihiko Yoshimasu
Keyword(s):  
Power Amplifier ◽  
High Efficiency ◽  
Low Voltage ◽  
Supply Voltage ◽  
Drain Current ◽  
Cmos Technology ◽  
Back Gate ◽  
Third Harmonic ◽  
Power Added Efficiency ◽  
Switching Transistor

This paper presents a 2.5-GHz low-voltage, high-efficiency CMOS power amplifier (PA) IC in 0.18-µm CMOS technology. The combination of a dual-switching transistor (DST) and a third harmonic tuning technique is proposed. The DST effectively improves the gain at the saturation power region when the additional gain extension of the secondary switching transistor compensates for the gain compression of the primary one. To achieve high-efficiency performance, the third harmonic tuning circuit is connected in parallel to the output load. Therefore, the flattened drain current and voltage waveforms are generated, which in turn reduce the overlapping and the dc power consumption significantly. In addition, a 0.5-V back-gate voltage is applied to the primary switching transistor to realize the low-voltage operation. At 1 V of supply voltage, the proposed PA has achieved a power added efficiency (PAE) of 34.5% and a saturated output power of 10.1 dBm.

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