Die Stacking (3D) Microarchitecture

2006 ◽  
Author(s):  
Bryan Black ◽  
Daniel Pantuso ◽  
Paul Reed ◽  
Jeff Rupley ◽  
Sadasivan Shankar ◽  
...  
Keyword(s):  
Die Stacking

Thin die stacking by low temperature In/ Au IMC based bonding method

2009 ◽  
Author(s):  
Siong Chiew Ong ◽  
Won Kyoung Choi ◽  
C. S. Premachandran ◽  
Ebin Liao ◽  
Ling Xie
Keyword(s):  
Low Temperature ◽  
Die Stacking ◽  
Bonding Method

Reactivation of Spares for Off-Chip Memory Repair After Die Stacking in a 3-D IC With TSVs

2013 ◽  
Vol 60 (9) ◽  
pp. 2343-2351 ◽  
Author(s):  
Yung-Fa Chou ◽  
Ding-Ming Kwai ◽  
Ming-Der Shieh ◽  
Cheng-Wen Wu
Keyword(s):  
Die Stacking ◽  
Memory Repair

Optical transceiver ICs based on 3D die-stacking of optoelectronic devices

2014 ◽  
Author(s):  
H. J. S. Dorren ◽  
P. Duan ◽  
O. Raz
Keyword(s):  
Optoelectronic Devices ◽  
Die Stacking

Challenges and approaches of TSV thin die stacking on organic substrate

2011 ◽  
Author(s):  
Sharon Lim Pei-Siang ◽  
Che Faxing ◽  
Chong Ser Choong ◽  
Michelle Chew Bi Rong ◽  
Vasarla Nagendra Sekhar ◽  
...  
Keyword(s):  
Organic Substrate ◽  
Die Stacking

Die to Wafer Hybrid Bonding: Multi-Die Stacking with Tsv Integration

2020 ◽  
Author(s):  
Guilian Gao ◽  
Jeremy Theil ◽  
Gill Fountain ◽  
Thomas Workman ◽  
Gabe Guevara ◽  
...  
Keyword(s):  
Die Stacking

Next Generation Electrochemical Deposition TSV Fill

2014 ◽  
Vol 2014 (DPC) ◽  
pp. 001523-001535
Author(s):  
Bioh Kim ◽  
Stephen Golovato ◽  
Tyler Barbera ◽  
Keiichi Fujita ◽  
Takashi Tanaka
Keyword(s):  
Aspect Ratio ◽  
Electrochemical Deposition ◽  
Vapor Deposition ◽  
Physical Vapor Deposition ◽  
Chemical Vapor ◽  
Scale Production ◽  
Next Generation ◽  
Typical Structure ◽  
Die Stacking ◽  
Seed Deposition

The first generation of through silicon via (TSV) designs for interposer and 3D die stacking has concentrated on TSV features with aspect ratio (AR) on the order of ten. Typical via sizes are 10 X 100 um for interposer and 5 X 50 um for 3D applications. Ionized physical vapor deposition (IPVD) has been successful in depositing barrier and seed layers in these AR=10 vias that allow efficient “bottom-up” filling by electrochemical deposition (ECD) using available chemistries. While these applications are currently moving to pilot lines and low scale production, research and development has already begun on the next generation of TSV structures for interposer and die stacking. These may be based on via middle or via last designs. They are expected to increase in aspect ratio for denser TSV arrays while maintaining similar wafer thickness. Structures with AR in the range of 15–20 are being designed and produced. For interposer, a typical structure might be 8 X 120 um and 2 X 40 um for 3D stacks. These structures will challenge all TSV formation processes, including etch, dielectric liner deposition, barrier-seed deposition and TSV fill. This paper will focus on barrier-seed and TSV fill processes. IPVD barrier-seed deposition will be difficult for AR~15–20 and will require much longer deposition times for complete via coverage. Long IPVD times will produce thick overburden and pinch off the opening at the top of vias. Even if successful, IPVD may not be viable economically. More conformal deposition processes, such as atomic layer deposition (ALD), chemical vapor deposition (CVD) and wet processes, like electro-less plating and conformal ECD, may be better alternatives to IPVD. A conformal process only needs to deposit the minimum required seed thickness in the via for successful ECD filling with the overburden being nearly the same thickness. The development of a successful conformal barrier-seed process may even challenge IPVD for AR=10. This paper presents ECD TSV fill results using several conformal barrier-seed processes, demonstrating the feasibility of this approach for structures with AR = 10–20.

Bonding Technologies for 3D integration

2015 ◽  
Vol 2015 (1) ◽  
pp. 000231-000234
Author(s):  
Sascha Lohse ◽  
Alexander Wollanke
Keyword(s):  
Flip Chip ◽  
Process Technology ◽  
3D Integration ◽  
Test Procedures ◽  
Fine Pitch ◽  
Ic Packaging ◽  
Die Stacking ◽  
3D Packaging ◽  
Small Bump ◽  
Suitable Process

Tougher requirements related to the request for smaller, lighter and multi-functional electronic devices impose increased demands on IC packaging. Ever more complex circuitry, fine pitch and micro bump designs and die stacking are examples of how the industry meets these demands. Finding a suitable process technology for 3D packaging can be a challenge. This paper provides information about various connection methods predominantly used in today's 3D packaging. In comprehensive trials, various dies characterized by high bump count (up to 143,000), fine pitch (down to 25 μm) and small bump diameter (down to 13 μm) were placed on a substrate using a semi-automated flip chip bonder. This whitepaper describes test procedures for different 3D integration technologies and presents utilized process parameters and results.

Underfill Dispensing for 3D Die Stacking with Through Silicon Vias

2012 ◽  
Vol 2012 (1) ◽  
pp. 000548-000553 ◽  
Author(s):  
Fuliang Le ◽  
S. W. Ricky Lee ◽  
Jingshen Wu ◽  
Matthew M. F. Yuen
Keyword(s):  
Flip Chip ◽  
Through Silicon Vias ◽  
Flip Chips ◽  
Solder Bumps ◽  
Die Stacking ◽  
Chip Carrier ◽  
On Chip ◽  
Silicon Vias ◽  
3D Package

In this paper, a 3D stacked-die package is developed for the miniaturization and integration of electronic devices. The developed package has a stacked flip-chip-on-chip structure and eight flip chips are arranged in four vertical layers using four silicon chip carriers with through silicon vias (TSVs). In each layer, two flip chips are mounted on the silicon chip carrier with 100 um solder bumps, and multiple TSVs are fabricated in each silicon chip carrier for underfill dispensing purpose. The 3D module with four stacked layers is sequentially assembled by the standard surface mount reflow process and finally mounted to a substrate. In the underfill process, conventional I-pass underfill is used to fill up the gaps of the bottom two layers as it has relatively fast spreading speed. For the top two chip carriers, underfill is dispensed through TSVs to fill the gaps. Unlike the conventional underfill process, the encapsulant in this case would not flow in the gaps by the capillary effect unless the dispensed materials can obtain enough kinetic energy to overcome the surface tension at the end of TSVs, and thus, smooth sidewall, proper dispensing settings and optimized TSV pattern are needed. After underfill, detailed inspections are performed to verify the quality of encapsulation. The results show that the combined I-pass/TSV underfill process gives void-free encapsulation and perfect fillets for the stacked 3D package.

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