scholarly journals Mitigating the Impact of Process Variations on Processor Register Files and Execution Units

2006 ◽  
Author(s):  
Xiaoyao Liang ◽  
David Brooks
Keyword(s):  
Process Variations ◽  
Register Files ◽  
The Impact

Design of a Robust Memristive Spiking Neuromorphic System with Unsupervised Learning in Hardware

2021 ◽  
Vol 17 (4) ◽  
pp. 1-26
Author(s):  
Md Musabbir Adnan ◽  
Sagarvarma Sayyaparaju ◽  
Samuel D. Brown ◽  
Mst Shamim Ara Shawkat ◽  
Catherine D. Schuman ◽  
...  
Keyword(s):  
Unsupervised Learning ◽  
Recognition Task ◽  
Single Layer ◽  
Process Variations ◽  
Spike Timing ◽  
System Level ◽  
Design Parameters ◽  
Digital Pulse ◽  
Neuromorphic System ◽  
The Impact

Spiking neural networks (SNN) offer a power efficient, biologically plausible learning paradigm by encoding information into spikes. The discovery of the memristor has accelerated the progress of spiking neuromorphic systems, as the intrinsic plasticity of the device makes it an ideal candidate to mimic a biological synapse. Despite providing a nanoscale form factor, non-volatility, and low-power operation, memristors suffer from device-level non-idealities, which impact system-level performance. To address these issues, this article presents a memristive crossbar-based neuromorphic system using unsupervised learning with twin-memristor synapses, fully digital pulse width modulated spike-timing-dependent plasticity, and homeostasis neurons. The implemented single-layer SNN was applied to a pattern-recognition task of classifying handwritten-digits. The performance of the system was analyzed by varying design parameters such as number of training epochs, neurons, and capacitors. Furthermore, the impact of memristor device non-idealities, such as device-switching mismatch, aging, failure, and process variations, were investigated and the resilience of the proposed system was demonstrated.

scholarly journals Dynamic and Static Calibration of Ultra-Low-Voltage, Digital-Based Operational Transconductance Amplifiers

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 983 ◽  
Author(s):  
Pedro Toledo ◽  
Paolo Crovetti ◽  
Hamilton Klimach ◽  
Sergio Bampi
Keyword(s):  
Pulse Width Modulation ◽  
Low Voltage ◽  
Process Variations ◽  
Pulse Modulation ◽  
Silicon Area ◽  
Operational Transconductance Amplifiers ◽  
Static Calibration ◽  
Digital Pulse ◽  
Transconductance Amplifiers ◽  
The Impact

The calibration of the effects of process variations and device mismatch in Ultra Low Voltage (ULV) Digital-Based Operational Transconductance Amplifiers (DB-OTAs) is addressed in this paper. For this purpose, two dynamic calibration techniques, intended to dynamically vary the effective strength of critical gates by different modulation strategies, i.e., Digital Pulse Width Modulation (DPWM) and Dyadic Digital Pulse Modulation (DDPM), are explored and compared to classic static calibration. The effectiveness of the calibration approaches as a mean to recover acceptable performance in non-functional samples is verified by Monte-Carlo (MC) post-layout simulations performed on a 300 mV power supply, nW-power DB-OTA in 180 nm CMOS. Based on the same MC post-layout simulations, the impact of each calibration strategy on silicon area, power consumption, and OTA performance is discussed.

Impact of Device Variability and Circuit Phase Shift in Synchronized Spin Torque Oscillators

2007 ◽  
Vol 998 ◽  
Author(s):  
Johan Persson ◽  
Yan Zhou ◽  
Johan Akerman
Keyword(s):  
Phase Diagram ◽  
Time Delay ◽  
Process Variations ◽  
Small Time ◽  
Spin Transfer Torque ◽  
Spin Torque ◽  
Plane Anisotropy ◽  
Out Of Plane ◽  
The Impact ◽  
Spin Torque Oscillators

ABSTRACTCurrent-induced magnetization dynamics in a system composed of two electrically coupled spin torque oscillators (STOs) is examined. The dynamics of the STOs is modeled by the Landau–Lifshitz–Gilbert equations modified with a Slonczewski spin-transfer torque term. To study the impact of realistic process variations on STO synchronization we let the two STOs have different in-plane anisotropy fields (Hk). The simulation also provides for a time delay τ. We construct a phase diagram of the STO synchronization as a function of Hk and direct current (Idc) at different τ. The phase diagram turns out to be quite rich with different types of synchronized precession modes. While the synchronized state is originally very sensitive to STO process variations and can only sustain up to 4% Hk variation, the addition of a small time delay dramatically improves its robustness and allows as much as 145% Hk variation in the entire out-of-plane precession regime. It is also shown that the two STOs can not only be locked in frequency, but also in phase at a given τ and the phase difference between the two STOs can be tuned by varying the dc current.

A Table-Based Approach to Study the Impact of Process Variations on FinFET Circuit Performance

2010 ◽  
Vol 29 (4) ◽  
pp. 627-631 ◽  
Author(s):  
Rajesh A. Thakker ◽  
Chaitanya Sathe ◽  
Maryam Shojaei Baghini ◽  
Mahesh B. Patil
Keyword(s):  
Process Variations ◽  
Circuit Performance ◽  
The Impact

Experimental Investigation on the Efficiency of a Control Dependent NiTi-Based Cooling Process

2014 ◽  
Author(s):  
Marvin Schmidt ◽  
Andreas Schütze ◽  
Stefan Seelecke
Keyword(s):  
Energy Efficient ◽  
Cooling System ◽  
Experimental Testing ◽  
Control Process ◽  
Process Variations ◽  
Coefficient Of Performance ◽  
Testing System ◽  
Cooling Process ◽  
Commercial Development ◽  
The Impact

Energy efficient systems and environmentally friendly solutions are the focus of many commercial development projects. Current refrigeration technology carries a significant share of global energy consumption and exploring alternative refrigeration principles has become increasingly important. Shape memory alloys (SMA’s), especially Nickel-Titanium (NiTi) alloys, generate a large amount of latent heat during solid-state phase transformations, which can lead to a significant cooling effect in the material. These materials not only provide the potential for an energy efficient cooling process, they also minimize the impact on the environment by reducing the need for conventional ozone-depleting refrigerants. This paper presents the first experimental results obtained in a project within the DFG Priority Programme SPP 1599 “Ferroic Cooling”. It focuses on the performance of a control-dependent process of a NiTi-based cooling system. First, a suitable cooling process is introduced and the underlying mechanisms of the process are explained. Then different process variations are developed, which influence the efficiency of the cooling process. These process variations are systematically analyzed with a novel, experimental testing system capable of tuning process parameters independently. The testing system is able to measure force, displacement, temperature distribution and heat simultaneously. The coefficient of performance (of the cooling process) can then be determined by which the influence of the control process on the efficiency can be observed.

scholarly journals Device reliability challenges for modern semiconductor circuit design – a review

2009 ◽  
Vol 7 ◽  
pp. 201-211 ◽  
Author(s):  
C. Schlünder
Keyword(s):  
Technology Development ◽  
Circuit Simulation ◽  
Safety Margin ◽  
Process Variations ◽  
Carrier Injection ◽  
Design For Reliability ◽  
Operation Conditions ◽  
Product Lifetime ◽  
The Difference ◽  
The Impact

Abstract. Product development based on highly integrated semiconductor circuits faces various challenges. To ensure the function of circuits the electrical parameters of every device must be in a specific window. This window is restricted by competing mechanisms like process variations and device degradation (Fig. 1). Degradation mechanisms like Negative Bias Temperature Instability (NBTI) or Hot Carrier Injection (HCI) lead to parameter drifts during operation adding on top of the process variations. The safety margin between real lifetime of MOSFETs and product lifetime requirements decreases at advanced technologies. The assignment of tasks to ensure the product lifetime has to be changed for the future. Up to now technology development has the main responsibility to adjust the technology processes to achieve the required lifetime. In future, reliability can no longer be the task of technology development only. Device degradation becomes a collective challenge for semiconductor technologist, reliability experts and circuit designers. Reliability issues have to be considered in design as well to achieve reliable and competitive products. For this work, designers require support by smart software tools with built-in reliability know how. Design for reliability will be one of the key requirements for modern product designs. An overview will be given of the physical device damage mechanisms, the operation conditions within circuits leading to stress and the impact of the corresponding device parameter degradation on the function of the circuit. Based on this understanding various approaches for Design for Reliability (DfR) will be described. The function of aging simulators will be explained and the flow of circuit-simulation will be described. Furthermore, the difference between full custom and semi custom design and therefore, the different required approaches will be discussed.

scholarly journals Impact of PCB Manufacturing Process Variations on Trace Impedance

2011 ◽  
Vol 2011 (1) ◽  
pp. 000891-000895 ◽  
Author(s):  
Abdelghani Renbi ◽  
Johan Carlson ◽  
Jerker Delsing
Keyword(s):  
Phase Shift ◽  
Manufacturing Process ◽  
Characteristic Impedance ◽  
Process Variations ◽  
P Values ◽  
Pcb Manufacturing ◽  
The Mean ◽  
The Difference ◽  
The Impact ◽  
Measured Phase

This paper demonstrates statistically the impact of PCB manufacturing variations on the characteristic impedance. Moreover, it shows that the characteristics of the PCBs vary across different suppliers. These differences cannot be tolerated in some applications where the characteristic impedance is restricted to be within a specific range. We sampled 3 × 20 PCBs, each batch of twenty is ordered from a different manufacturer. The sampling consist of measuring the phase shift between the reected and the incident signals when injecting a 180 MHz sinewave into a PCB trace. The trace is selected to be the same for all samples. All the PCBs are ordered to be identical and designed for 50 Ω devices. Our conclusion was drawn after running the T-tests to assess statistically the significance of the difference occurring between the PCBs. Based on the computed P-values all the three batches are different from each other in the mean of the measured phase shift with 95 % confidence. The difference between the measured and the expected characteristic impedance is found as 3 %, 10 % and 20 % for these three manufacturers. We also witnessed board-to-board variations even within the same batch and from the same supplier due to the process instability by looking at the probability density of having the same phase shift that is equal to the mean. Some samples shown 2.6 % to 3.5 % difference above the mean.

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