Digitally controlled CMOS quadrature ring oscillator with improved FoM for GHz range all-digital phase-locked loop applications

The paper reviews working principles of phase-locked loop and drawbacks of classical PLL structure in nanometric technologies. It is proposed to replace the classical structure by all-digital phase-locked loop structure. Authors described the main blocks of all-digital phase-locked loop (time to digital converter and digitally controlled oscillator) and overviewed the quantization noise arising in these blocks as well as its minimization strategies. The calculated inverter delay in 65 nm CMOS technology was from 8.64 to 27.71 ps and time to digital converter quantization noise was from −104.33 to −82.17 dBc/Hz, with tres = 8.64–27.71 ps, TSVG = 143–333 ps, FREF = 20–60 MHz. Article in Lithuanian. Santrauka Nagrinėjama fazės derinimo kilpa (FDK), jos veikimas, klasikinės struktūros FDK trūkumai nanometrinėse technologijose, galimi jų sprendimo būdai. Siūlomas perėjimas prie visiškai skaitmeninės fazės derinimo kilpos. Aprašomi pagrindiniai visiškai skaitmeninės FDK blokai – laikinis skaitmeninis keitiklis (LSK) ir skaitmeniniu būdu valdomas generatorius (SVG). Aptariamas LSK ir SVG atsirandantis kvantavimo triukšmas ir jo mažinimo priemonės. Apskaičiuota 65 nm KMOP technologijoje pasiekiama inverterio vėlinimo trukmė, lygi nuo 8,64 iki 27,71 ps, ir LSK triukšmo lygis, lygus nuo −104,33 iki −82,17 dBc/Hz, kai inverterio vėlinimo trukmė t res = 8,64–27,71 ps, SVG generuojamo signalo periodas TSVG = 143–333 ps, o atraminio signalo dažnis FREF = 20–60 MHz.

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Design and Emulation of All-Digital Phase-Locked Loop on FPGA

Electronics ◽

10.3390/electronics8111307 ◽

2019 ◽

Vol 8 (11) ◽

pp. 1307 ◽

Cited By ~ 1

Author(s):

Saichandrateja Radhapuram ◽

Takuya Yoshihara ◽

Toshimasa Matsuoka

Keyword(s):

Tuning Range ◽

Ring Oscillator ◽

Frequency Resolution ◽

Design Stage ◽

Early Design Stage ◽

Digital Phase ◽

Delta Sigma ◽

Wide Range ◽

Digitally Controlled ◽

Time Required

This paper demonstrates the design and implementation of an all-digital phase-lockedloop (ADPLL) on Field Programmable Gate Array (FPGA). It is useful as an emulation techniqueto show the feasibility and effectiveness of the ADPLL in the early design stage. A D-S modulator(DSM, Delta-Sigma Modulator)-based digitally controlled ring-oscillator (ring-DCO) design, whichis fully synthesizable in Verilog HDL, is presented. This ring-DCO has fully digital control andfractional tuning range using the DSM. The ring-DCO does not contain library-specific cells andcan be synthesized independently of the standard cell library, thus making the design portable andreducing the time required to fit for different semiconductor processes considerably. Implementedring-DCO has a wide tuning range and high-frequency resolution which meet the demands ofsystem-level integration. The ADPLL implemented in this work has the characteristics of designflexibility, a wide range of working frequency from 120 MHz to 300 MHz, and a fast responsefor achieving a locked state. The proposed ADPLL can be easily ported to different processes ina short time. The design adaptation cost is limited to adjustment of loop parameters in the code.Thus, it can reduce the design time and design complexity of the ADPLL, making it very suitable forSystem-on-Chip (SoC) applications.

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Design of All Digital Phase Locked Loop for Wireless Applications

International Journal of Engineering & Technology ◽

10.14419/ijet.v7i3.12.16513 ◽

2018 ◽

Vol 7 (3.12) ◽

pp. 836

Author(s):

Swetha R ◽

J Manjula ◽

A Ruhan bevi

Keyword(s):

Frequency Synthesizer ◽

Phase Locked Loop ◽

Cmos Technology ◽

Phase Detector ◽

Ring Oscillator ◽

Frequency Range ◽

Loop Filter ◽

Wireless Applications ◽

Digital Phase ◽

Operating Frequency Range

This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO). The programmable divider is used in the feed-back loop which is used has a frequency synthesizer for wireless applications. It is implemented in 180nm CMOS technology in Cadence EDA tool. The proposed ADPLL has locking period of 50ps and the operating frequency range of 4.7GHz and power consumption of 26mW.

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A Low-Power Digitally Controlled Oscillator for All Digital Phase-Locked Loops

VLSI Design ◽

10.1155/2010/946710 ◽

2010 ◽

Vol 2010 ◽

pp. 1-11 ◽

Cited By ~ 11

Author(s):

Jun Zhao ◽

Yong-Bin Kim

Keyword(s):

Low Power ◽

Supply Voltage ◽

Schmitt Trigger ◽

Ring Oscillator ◽

Phase Locked Loops ◽

Digital Phase ◽

Digitally Controlled ◽

Low Power Cmos ◽

Digitally Controlled Oscillator ◽

Lock In

A low-power and low-jitter 12-bit CMOS digitally controlled oscillator (DCO) design is presented. The Low-Power CMOS DCO is designed based on the ring oscillator implemented with Schmitt trigger inverters. The proposed DCO circuit uses control codes of thermometer type to reduce jitters. Performance of the DCO is verified through a novel All Digital Phase-Locked Loop (ADPLL) designed with a unique lock-in process by employing a time-to-digital converter, where both the frequency of the reference clock and the delay between DCO_output and DCO_clock is measured. A carefully designed reset process reduces the phase acquisition process to two cycles. The ADPLL was implemented using the 32 nm Predictive Technology Model (PTM) at 0.9 V supply voltage, and the simulation results show that the proposed ADPLL achieves 10 and 2 reference cycles of frequency and phase acquisitions, respectively, at 700 MHz with less than 67 ps peak-to-peak jitter. The DCO consumes 2.2 mW at 650 MHz with 0.9 V power supply.

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