Performance Analysis of Low Power Low Voltage Amplifier Designs in 45nm CMOS Technology by Incorporating Miller Compensation

2020 ◽  
Author(s):  
Lakshmy V ◽  
Shajahan E S
Keyword(s):  
Performance Analysis ◽  
Low Power ◽  
Low Voltage ◽  
Cmos Technology ◽  
Miller Compensation ◽  
Voltage Amplifier

Design of Low Voltage Low Power LPF for WSN Node

2013 ◽  
Vol 760-762 ◽  
pp. 54-59
Author(s):  
Yang Lin ◽  
Zhi Qun Li ◽  
Chen Jian Wu ◽  
Meng Zhang ◽  
Zeng Qi Wang
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Frequency Tuning ◽  
Cmos Technology ◽  
Pass Band ◽  
Automatic Frequency ◽  
Temperature Deviation ◽  
Op Amp ◽  
Active Rc Filter ◽  
Operation Amplifier

A fourth-order low-pass continuous-time filter for a WSN transmitter is presented. The active RC filter was chosen for the high linearity, designed by using the leapfrog topology imitates the passive filter. The operation amplifier (op-amp) adopted by the filter is feed-forward operation amplifier, which could get the GBW as large as possible under the low power consumption. The cut-off frequency deviation due to the process corner, aging and temperature deviation is adjusted by an automatic frequency tuning circuit. The filter in a 0.18μm RF CMOS technology consumes 1mW from a 1V power supply. The measured results of the chip show that the bandwidth is about 1.5MHz. The voltage gain of filter is about-4.5dB with the buffer, the ripple in the pass-band is lower than 0.5 dB, and the channel rejection ratio is larger than 30dB at 4MHz.

scholarly journals A 2.5 Gbps, 10-Lane, Low-Power, LVDS Transceiver in 28 nm CMOS Technology

Electronics ◽  
2019 ◽  
Vol 8 (3) ◽  
pp. 350 ◽  
Author(s):  
Xu Bai ◽  
Jianzhong Zhao ◽  
Shi Zuo ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
High Speed ◽  
Low Voltage ◽  
Cmos Technology ◽  
Common Mode ◽  
Serial Interface ◽  
Common Mode Voltage ◽  
Rail To Rail ◽  
The Common ◽  
28 Nm

This paper presents a 2.5 Gbps 10-lane low-power low voltage differential signaling (LVDS) transceiver for a high-speed serial interface. In the transmitter, a complementary MOS H-bridge output driver with a common mode feedback (CMFB) circuit was used to achieve a stipulated common mode voltage over process, voltage and temperature (PVT) variations. The receiver was composed of a pre-stage common mode voltage shifter and a rail-to-rail comparator. The common mode voltage shifter with an error amplifier shifted the common mode voltage of the input signal to the required range, thereby the following rail-to-rail comparator obtained the maximum transconductance to recover the signal. The chip was fabricated using SMIC 28 nm CMOS technology, and had an area of 1.46 mm2. The measured results showed that the output swing of the transmitter was around 350 mV, with a root-mean-square (RMS) jitter of 3.65 [email protected] Gbps, and the power consumption of each lane was 16.51 mW under a 1.8 V power supply.

Low Voltage Low Power Up-Conversion Mixer for Wireless Sensor Networks Node Application

2013 ◽  
Vol 760-762 ◽  
pp. 516-520
Author(s):  
Ge Sun ◽  
Zhi Qun Li ◽  
Chen Jian Wu ◽  
Meng Zhang ◽  
Jia Cao ◽  
...  
Keyword(s):  
Wireless Sensor Networks ◽  
Sensor Networks ◽  
Low Power ◽  
Low Voltage ◽  
Noise Figure ◽  
Cmos Technology ◽  
Negative Resistance ◽  
Wireless Sensor ◽  
Operating Voltage ◽  
Conversion Gain

A low voltage, low power up-conversion mixer is presented here for 2.4GHz wireless sensor networks (WSN). It was based on a double-balanced Gilbert cell type. The current-reuse technique was used to reduce the power consumption and negative-resistance compensation technique was used to improve the conversion gain. The mixer was designed in 0.18μm RF CMOS technology, and was simulated with Cadence SpectreRF. The simulation results indicate that the conversion gain is 6.37dB, the noise figure is 15.36dB and the input 1dB compression point is-10.3dBm, while consuming 1mA current for operating voltage at 1V.

AN ULTRA LOW-VOLTAGE/POWER-EFFICIENT ALL-DIGITAL DELAY LOCKED LOOP IN 55 nm CMOS TECHNOLOGY

2012 ◽  
Vol 21 (08) ◽  
pp. 1240025 ◽  
Author(s):  
CHUN-YUAN CHENG ◽  
JINN-SHYAN WANG ◽  
CHENG-TAI YEH
Keyword(s):  
Low Power ◽  
Power Dissipation ◽  
Low Voltage ◽  
Cmos Technology ◽  
Maximum Frequency ◽  
Clock Frequency ◽  
Power Efficient ◽  
Delay Locked Loop ◽  
Measurement Results ◽  
Variation Tolerance

This paper presents an all-digital delay locked loop (ADDLL) that uses asynchronous-deskewing technology and achieves low power/voltage, small jitter, fast locking, and high process, voltage, and temperature (PVT)-variation tolerance. The measurement results show that the maximum frequency is 100 MHz at 0.35 V with 19 μW power dissipation, 62 ps peak-to-peak jitter, and 3 locking cycles. When operated at 0.5 V, the measured maximal operating clock frequency is 450 MHz with 12 ps peak-to-peak jitter, 6 locking cycles and 119 μW power dissipation. The ADDLL is fabricated with 55 nm CMOS technology, and the active area is only 0.019 mm2.

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