22nm Ultra-Thin Body and Buried Oxide FDSOI RF Noise Performance

This work analyzes the third generation BESOI MOSFET (Back-Enhanced Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-transistor) built on UTBB (Ultra-Thin Body and Buried Oxide), comparing it to the BESOI with thick buried oxide (first generation). The stronger coupling between front and back interfaces of the UTBB BESOI device improves in 67% the current drive, 122% the maximum transconductance and 223% the body factor. Operating with seven times lower back gate bias, the UTBB BESOI MOSFET presented more compatibility with standard SOI CMOS (Complementary MOS) technology than the BESOI with thick buried oxide.

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Analysis of RF noise performance of Si/SiGe pseudomorphic MOSFETs

2009 Spanish Conference on Electron Devices ◽

10.1109/sced.2009.4800538 ◽

2009 ◽

Author(s):

Jaime Calvo-Gallego ◽

Kristel Fobelets ◽

J.E. Velazquez Perez

Keyword(s):

Noise Performance ◽

Rf Noise

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Low leakage and low variability Ultra-Thin Body and Buried Oxide (UT2B) SOI technology for 20nm low power CMOS and beyond

2010 Symposium on VLSI Technology ◽

10.1109/vlsit.2010.5556122 ◽

2010 ◽

Cited By ~ 33

Author(s):

F. Andrieu ◽

O. Weber ◽

J. Mazurier ◽

O. Thomas ◽

J-P. Noel ◽

...

Keyword(s):

Low Power ◽

Thin Body ◽

Buried Oxide ◽

Low Leakage ◽

Low Power Cmos ◽

Soi Technology

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Ultra-thin body & buried oxide SOI substrate development and qualification for Fully Depleted SOI device with back bias capability

Solid-State Electronics ◽

10.1016/j.sse.2015.11.008 ◽

2016 ◽

Vol 117 ◽

pp. 2-9 ◽

Cited By ~ 12

Author(s):

Walter Schwarzenbach ◽

Bich-Yen Nguyen ◽

Frederic Allibert ◽

Christophe Girard ◽

Christophe Maleville

Keyword(s):

Thin Body ◽

Fully Depleted ◽

Buried Oxide

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Substrate Effect Evaluation by the Analysis of Intrinsic Capacitances in SOI UTBB Transistors

Journal of Integrated Circuits and Systems ◽

10.29292/jics.v15i1.118 ◽

2020 ◽

Vol 15 (1) ◽

pp. 1-6

Author(s):

Fernando José Costa ◽

Renan Trevisoli Doria ◽

Rodrigo Trevisoli Doria

Keyword(s):

Experimental Data ◽

Ground Plane ◽

Capacitive Coupling ◽

Thin Body ◽

Substrate Effect ◽

Gate Bias ◽

Effect Evaluation ◽

Back Gate ◽

Buried Oxide

The main goal of this paper is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with respect to the back gate bias (VSUB) through DC and AC simulations validated to experimental data. Different ground plane (GP) arrangements have been considered in order to enhance the analysis. It has been shown that the substrate effect is strongly influenced by the reduction of the back gate bias and, that the capacitive coupling of the structure presents a different behavior with respect of each kind of GP configuration as the back gate bias is varied. Finally, it has been shown that the GP below the source and drain regions contributes significantly to the overall capacitive coupling of the transistors.

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