Variability of planar Ultra-Thin Body and Buried oxide (UTBB) FDSOI MOSFETs

Author(s):  
J. Mazurier ◽  
O. Weber ◽  
F. Andrieu ◽  
C. Le Royer ◽  
O. Faynot ◽  
...  
Keyword(s):  
2016 ◽  
Vol 117 ◽  
pp. 100-116 ◽  
Author(s):  
Pierre Morin ◽  
Sylvain Maitrejean ◽  
Frederic Allibert ◽  
Emmanuel Augendre ◽  
Qing Liu ◽  
...  

2020 ◽  
Vol 15 (1) ◽  
pp. 1-6
Author(s):  
Ricardo Cardoso Rangel ◽  
Katia R. A. Sasaki ◽  
Leonardo Shimizu Yojo ◽  
João Antonio Martino

This work analyzes the third generation BESOI MOSFET (Back-Enhanced Silicon-On-Insulator Metal-Oxide-Semiconductor Field-Effect-transistor) built on UTBB (Ultra-Thin Body and Buried Oxide), comparing it to the BESOI with thick buried oxide (first generation). The stronger coupling between front and back interfaces of the UTBB BESOI device improves in 67% the current drive, 122% the maximum transconductance and 223% the body factor. Operating with seven times lower back gate bias, the UTBB BESOI MOSFET presented more compatibility with standard SOI CMOS (Complementary MOS) technology than the BESOI with thick buried oxide.


2016 ◽  
Vol 117 ◽  
pp. 2-9 ◽  
Author(s):  
Walter Schwarzenbach ◽  
Bich-Yen Nguyen ◽  
Frederic Allibert ◽  
Christophe Girard ◽  
Christophe Maleville

2020 ◽  
Vol 15 (1) ◽  
pp. 1-6
Author(s):  
Fernando José Costa ◽  
Renan Trevisoli Doria ◽  
Rodrigo Trevisoli Doria

The main goal of this paper is to present the behavior of the substrate effect in Ultra-Thin Body and Buried Oxide (UTBB) SOI MOSFETs with respect to the back gate bias (VSUB) through DC and AC simulations validated to experimental data. Different ground plane (GP) arrangements have been considered in order to enhance the analysis. It has been shown that the substrate effect is strongly influenced by the reduction of the back gate bias and, that the capacitive coupling of the structure presents a different behavior with respect of each kind of GP configuration as the back gate bias is varied. Finally, it has been shown that the GP below the source and drain regions contributes significantly to the overall capacitive coupling of the transistors.


Author(s):  
Ousmane M. Kane ◽  
Luca Lucci ◽  
Pascal Scheiblin ◽  
Sylvie Lepilliet ◽  
Francois Danneville

2015 ◽  
Vol 1109 ◽  
pp. 257-261 ◽  
Author(s):  
Noraini Othman ◽  
Mohd Khairuddin Md Arshad ◽  
Syarifah Norfaezah Sabki ◽  
U. Hashim

This paper reviews the different UTBB SOI MOSFET structures and their superiority in suppressing short-channel effects (SCEs). As the gate length (Lg), buried oxide thickness (TBOX) and silicon thickness (Tsi) are scaled down, the severity of SCEs becomes significant. The different UTBB SOI MOSFET device structures introduced to suppress these SCEs are discussed. The effectiveness of these structures in managing the associated SCEs such as drain-induced barrier lowering (DIBL), subthreshold swing (SS) and off-state leakage current (Ioff) is also presented. Further evaluations are made on other competing CMOS technologies such as multigate MOSFETs (FinFETs, three-gates, four-gates) and junctionless transistor in controlling the SCEs.


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