A CMOS integrated circuit for DNA hybridization detection with digital output and temperature control

Author(s):  
Alessandra Caboni ◽  
Daniela Loi ◽  
Massimo Barbaro
Langmuir ◽  
2018 ◽  
Vol 34 (49) ◽  
pp. 14817-14824 ◽  
Author(s):  
Leila Zarei ◽  
Roya Tavallaie ◽  
Moinul H. Choudhury ◽  
Stephen G. Parker ◽  
Padmavathy Bakthavathsalam ◽  
...  

2015 ◽  
Vol 24 (09) ◽  
pp. 1550144 ◽  
Author(s):  
Ludovico Minati

A novel chaotic oscillator based on "cross-coupled" inverter rings is presented. The oscillator consists of a 3-ring to which higher odd n-rings are progressively coupled via diodes and pass gates; it does not contain reactive or resistive elements, and is thus suitable for area-efficient implementation on a CMOS integrated circuit. Numerical simulation based on piece-wise linear approximation predicted the generation of positive spikes having approximately constant periodicity but highly variable cycle amplitude. Simulation Program with Integrated Circuit Emphasis (SPICE) simulations and experimental data from a prototype realized on 0.7 μm technology confirmed this finding, and demonstrated increasing correlation dimension (D2) as 5-, 7- and 9-rings were progressively coupled to the 3-ring. Experimental data from a ring of 24 such oscillator cells showed phase synchronization and partial amplitude synchronization (formation of small clusters), emerging depending on DC gate voltage applied at NMOS transistors implementing diffusive coupling between neighboring cells. Thanks to its small area, simple synchronizability and digital controllability, the proposed circuit enables experimental investigation of dynamical complexity in large networks of coupled chaotic oscillators, and may additionally be suitable for applications such as broadband signal and random number generation.


2007 ◽  
Vol 1 (4) ◽  
pp. 367-376
Author(s):  
Sayyed Azimi ◽  
Mohammad Bahmanyar ◽  
Massoud Zolgharni ◽  
Wamadeva Balachandran

2014 ◽  
Vol 1693 ◽  
Author(s):  
David T. Clark ◽  
Robin F. Thompson ◽  
Aled E. Murphy ◽  
David A. Smith ◽  
Ewan P. Ramsay ◽  
...  

ABSTRACTWe present the characteristics of a high temperature CMOS integrated circuit process based on 4H silicon carbide designed to operate at temperatures beyond 300°C. N-channel and P-channel transistor characteristics at room and elevated temperatures are presented. Both channel types show the expected low values of field effect mobility well known in SiC MOSFETS. However the performance achieved is easily capable of exploitation in CMOS digital logic circuits and certain analogue circuits, over a wide temperature range.Data is also presented for the performance of digital logic demonstrator circuits, in particular a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. Devices are packaged in high temperature ceramic dual in line (DIL) packages, which are capable of greater than 300°C operation. A high temperature “micro-oven” system has been designed and built to enable testing and stressing of units assembled in these package types. This system heats a group of devices together to temperatures of up to 300°C while keeping the electrical connections at much lower temperatures. In addition, long term reliability data for some structures such as contact chains to n-type and p-type SiC and simple logic circuits is summarized.


2019 ◽  
Vol 30 (18) ◽  
pp. 184002 ◽  
Author(s):  
Ganesh Jayakumar ◽  
Maxime Legallais ◽  
Per-Erik Hellström ◽  
Mireille Mouis ◽  
Isabelle Pignot-Paintrand ◽  
...  

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