Full-wave RF Modeling of a Fan-Out Wafer-Level Packaging Technology Based on Al-Al Wafer Bonding

2020 ◽  
Author(s):  
M. Stocchi ◽  
M. Wietstruck ◽  
S. Schulze ◽  
C. Zhibo ◽  
S. Tolunay ◽  
...  
Keyword(s):  
Wafer Bonding ◽  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging ◽  
Full Wave

MEMS Wafer-level Packaging Technology Using LTCC Wafer

2012 ◽  
Vol 132 (8) ◽  
pp. 246-253 ◽  
Author(s):  
Mamoru Mohri ◽  
Masayoshi Esashi ◽  
Shuji Tanaka
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

Suspended high Q integrated inductor by wafer level packaging technology

2013 ◽  
Vol 21 (1) ◽  
pp. 215-219 ◽  
Author(s):  
M. Han ◽  
S. F. Wang ◽  
G. W. Xu ◽  
Le Luo
Keyword(s):  
Wafer Level ◽  
Packaging Technology ◽  
High Q ◽  
Integrated Inductor ◽  
Wafer Level Packaging

High Quality Integrated Inductor in Fan-out Wafer-Level Packaging Technology for mm-Wave Applications

2021 ◽  
Author(s):  
Kavin Senthil Murugesan ◽  
Mykola Chernobryvko ◽  
Sherko Zinal ◽  
Marco Rossi ◽  
Ivan Ndip ◽  
...  
Keyword(s):  
Wafer Level ◽  
High Quality ◽  
Packaging Technology ◽  
Integrated Inductor ◽  
Wafer Level Packaging

Electrical Chip-Board Interaction (e-CBI) of Wafer Level Packaging Technology

2017 ◽  
Vol 2017 (1) ◽  
pp. 000325-000330 ◽  
Author(s):  
Wei Zhao ◽  
Mark Nakamoto ◽  
Karthikeyan Dhandapani ◽  
Brian Henderson ◽  
Ron Lindley ◽  
...  
Keyword(s):  
Printed Circuit Board ◽  
Measured Data ◽  
Circuit Board ◽  
Wafer Level ◽  
Test Chip ◽  
Chip Design ◽  
Packaging Technology ◽  
Printed Circuit ◽  
Wafer Level Packaging ◽  
Simulation Results

Abstract Electrical Chip Board Interaction (e-CBI) has emerged as a new risk in chip design as silicon die can directly interact with printed circuit board (PCB) in substrate-less wafer level packaging technology. To assess this risk Qualcomm Technologies, Inc. has converted an existing test chip to wafer level packaging technology. Both the measured data and simulation results show that e-CBI risk is significant and must be carefully managed.

Development of a wafer level packaging technology for high voltage applications

2018 ◽  
Author(s):  
Marion Volpert ◽  
Abdenacer Aitmani ◽  
Adrien Gasse ◽  
Brigitte Soulier ◽  
Patrick Peray ◽  
...  
Keyword(s):  
High Voltage ◽  
Wafer Level ◽  
Packaging Technology ◽  
Wafer Level Packaging

Metal Wafer Bonding for MEMS Applications

2008 ◽  
Vol 1139 ◽  
Author(s):  
Viorel Dragoi ◽  
Gerald Mittendorfer ◽  
Franz Murauer ◽  
Erkan Cakmak ◽  
Eric Pabo
Keyword(s):  
Intermetallic Compound ◽  
Eutectic Alloy ◽  
Wafer Bonding ◽  
Alloy Layer ◽  
Manufacturing Processes ◽  
Wafer Level ◽  
Wafer Level Packaging ◽  
Metal Diffusion ◽  
Metal Layers ◽  
Different Levels

AbstractMetal layers can be used as bonding layers at wafer-level in MEMS manufacturing processes for device assembly as well as just for electrical integration of different levels. One has to distinguish between two main types of processes: metal diffusion bonding and bonding with formation of an interface eutectic alloy layer or an intermetallic compound. The different process principles determine also the applications area for each. From electrical interconnections to wafer-level packaging (with emphasis on vacuum packaging) metal wafer bonding is a very important technology in MEMS manufacturing processes.

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