Towards Novel Channel Doping Profiles in Short Channel Bulk MOSFETs for OFF-State Current Reduction and Superior Channel Electrostatics

Author(s):  
Harshit Kansal ◽  
Aditya Sankar Medury
1998 ◽  
Vol 532 ◽  
Author(s):  
Huilong Zhu

ABSTRACTA new physically-based model for reverse short channel effects has been developed. This kinetic model considers three species: neutral interstitial, immobile dopant and mobile interstitial-dopant pairs. To consider ion-implantation damage and stress effects on the Si/SiO2 interface, a non-uniform sink strength at the Si/SiO2 interface for interstitials has been assumed. ALAMODE, a PDE solver, was used to solve the model. Lateral boron distributions of NMOS devices in the channel near the Si/SiO2 interface have been simulated. Significant boron pile-up was found at the gate edges which is in quantitative agreement with the doping profiles extracted from experimental C-V data. The mechanism of the B diffusion in the channel region is discussed.


1997 ◽  
Vol 473 ◽  
Author(s):  
Samar K. Saha

ABSTRACTHot-carrier effect was studied for different channel doping profiles in nMOSFET devices with effective channel length near 100 nm using a device simulator. The test structures for device simulation were generated using gate oxide thickness of 3 nm. The channel doping profiles used were abrupt- and graded-retrograde types with low surface and high substrate concentrations, and conventional step profiles with high surface and low substrate concentrations. For accurate device simulation, a hydrodynamic model for semiconductors was used to simulate the non-local transport phenomena in the devices. The simulation results indicate that for ultra-short channel devices, the current drivability and the hot-carrier effects depend on the shape of channel doping profiles. For a given supply voltage, the hot-carrier effects in ultra-short channel devices can be controlled by optimizing the channel doping profiles.


1998 ◽  
Vol 514 ◽  
Author(s):  
K. Vasanth ◽  
P. Apte ◽  
J. Davis ◽  
S. Saxena ◽  
R. Burch ◽  
...  

ABSTRACTA modular approach to CMOS process development requires an understanding of individual process modules (channel, gate, etc.) and their interactions. The reverse short channel effect, (RSCE) in NMOS devices is one such interaction between the channel and source/drain (S/D) modules. Similarly the interaction between the S/D and silicide modules affects the contact and gate sheet resistance. This paper presents (a) an investigation of the effects of S/D processing (As and P implant conditions) on the RSCE, (b) effects of S/D and silicide processing on the contact and gate sheet resistance, (c) the use of an integrated system to optimize process modules and their interactions and (d) the validity of the modules and system in process development by obtaining a 4% improvement in drive current of a 0.25 micron NMOS device. The outputs of the S/D module include the doping profiles as a function of implant and anneal conditions. The interaction between the channel and S/D is caused by the damage created during the S/D implants, leading to channel dopant redistribution during subsequent thermal anneals. This interaction causes the RSCE in NMOS devices and has to be taken into account before the modules can be used for process optimization. The interaction is studied by varying the dose and energy of the As and P S/D implants and observing their effect of the RSCE. Further, to model this interaction, parameters of a 2D dopant profile model are extracted from device data and form a part of the S/D module in addition to the doping profile information. The system integrates the outputs from the process modules and their interactions and allows for a rapid search of the process space. The search criteria can be varied to include performance (e.g. drive and off current) and manufacturability criteria.


1982 ◽  
Vol 3 (9) ◽  
pp. 250-253 ◽  
Author(s):  
C.S. Balasubramanian ◽  
V. Jayakumar

1993 ◽  
Vol 3 (9) ◽  
pp. 1719-1728
Author(s):  
P. Dollfus ◽  
P. Hesto ◽  
S. Galdin ◽  
C. Brisset

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-761-C4-764
Author(s):  
D. CHEN ◽  
Z. LI
Keyword(s):  

2020 ◽  
Vol 140 (3) ◽  
pp. 175-183
Author(s):  
Kengo Kawauchi ◽  
Hayato Higa ◽  
Hiroki Watanabe ◽  
Keisuke Kusaka ◽  
Jun-ichi Itoh

2002 ◽  
Vol 715 ◽  
Author(s):  
Sang-Hoon Jung ◽  
Jae-Hoon Lee ◽  
Min-Koo Han

AbstractA short channel polycrystalline silicon thin film transistor (poly-Si TFT), which has single grain boundary in the center of channel, is reported. The reported poly-Si TFT employs lateral grain growth method through aluminum patterns, which acts as a selective beam mask and a lateral heat sink during the laser irradiation, on an amorphous silicon layer. The electrical characteristics of the proposed poly-Si TFT have been considerably improved due to grain boundary density lowered. The reported short channel poly-Si TFT with single grain boundary exhibits high mobility as 222 cm2/Vsec and large on/off current ratio exceeding 1 × 108.


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