Effect of Channel Profile Engineering on Hot Carrier Reliability in nMOSFETs with 100 nm Channel Lengths

1997 ◽  
Vol 473 ◽  
Author(s):  
Samar K. Saha
Keyword(s):  
Supply Voltage ◽  
High Surface ◽  
Device Simulation ◽  
Oxide Thickness ◽  
Channel Length ◽  
Short Channel ◽  
Hot Carrier ◽  
Hot Carrier Effects ◽  
Doping Profiles ◽  
Substrate Concentrations

ABSTRACTHot-carrier effect was studied for different channel doping profiles in nMOSFET devices with effective channel length near 100 nm using a device simulator. The test structures for device simulation were generated using gate oxide thickness of 3 nm. The channel doping profiles used were abrupt- and graded-retrograde types with low surface and high substrate concentrations, and conventional step profiles with high surface and low substrate concentrations. For accurate device simulation, a hydrodynamic model for semiconductors was used to simulate the non-local transport phenomena in the devices. The simulation results indicate that for ultra-short channel devices, the current drivability and the hot-carrier effects depend on the shape of channel doping profiles. For a given supply voltage, the hot-carrier effects in ultra-short channel devices can be controlled by optimizing the channel doping profiles.

Hot Carrier Effects in Deep Submicron Nmosfets

1996 ◽  
Vol 428 ◽  
Author(s):  
Abhijit Phanse ◽  
Samar Saha
Keyword(s):  
Electric Fields ◽  
Channel Length ◽  
Deep Submicron ◽  
Short Channel ◽  
Hot Carrier ◽  
Velocity Saturation ◽  
Substrate Current ◽  
Hot Carrier Effects ◽  
Saturation Effects ◽  
Channel Lengths

AbstractThis paper addresses hot-carrier related reliability issues in deep submicron silicon nMOSFET devices. In order to monitor the hot-carrier induced device degradation, the substrate current was measured for devices with varying channel lengths (20 um - 0.24 um) under various biasing conditions. Deep submicron devices experience velocity saturation of channel carriers due to extremely high lateral electric fields. To evaluate the effects of velocity saturation in the channel, the pinch-off length in the channel was extracted for all the devices of the target technology. It was observed that for very short channel devices, carriers in most of the channel experience velocity saturation and almost the entire channel gets pinched off. It is shown in this paper that for very short channel devices, the pinch-off length in the channel is limited by the effective channel length, and that velocity saturation effects are critical to the transport of channel carriers.

Hot Carrier Reliability in Sub-0.1 μm nMOSFET Devices

1996 ◽  
Vol 428 ◽  
Author(s):  
Samar K. Saha
Keyword(s):  
Impact Ionization ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Ionization Rate ◽  
Systematic Investigation ◽  
Short Channel ◽  
Carrier Heating ◽  
Hot Carrier ◽  
Carrier Effect ◽  
Channel Lengths

AbstractThis paper presents a systematic investigation of the hot-carrier effect in deep sub-micron silicon nMOSFET devices. A Hydrodynamic model for semiconductors was used to simulate the local carrier heating and the non-local transport phenomena in nMOSFETs of effective channel lengths 41, 66, 96, and 126 nrn under various biasing conditions. Test structures for device simulation were generated by using a super-steep retrograde channel profile with subsurface peak concentration of l×1018 cm−3, and a gate oxide thickness of 3 nm. Superb MOSFET device characteristics were obtained for all devices. The simulation results show a significant decrease in substrate current, electron impact ionization rate, and peak electron temperature near the drain end of the channel with the decrease in supply voltage. The distribution of electrons into the substrate due to local electron heating is shown to be responsible for hot-carrier reliability in ultra-short channel silicon nMOSFET devices.

scholarly journals Impact of device scaling on the electrical properties of MoS2 field-effect transistors

2021 ◽  
Vol 11 (1) ◽  
Author(s):  
Goutham Arutchelvan ◽  
Quentin Smets ◽  
Devin Verreck ◽  
Zubair Ahmed ◽  
Abhinav Gaur ◽  
...  
Keyword(s):  
Field Effect Transistors ◽  
Oxide Thickness ◽  
Channel Length ◽  
Contact Length ◽  
Power Performance ◽  
Semiconducting Materials ◽  
Large Area ◽  
Short Channel ◽  
Device Scaling ◽  
Performance Area

AbstractTwo-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices.

scholarly journals Comparative Simulation Analysis of Process Parameter Variations in 20 nm Triangular FinFET

2017 ◽  
Vol 2017 ◽  
pp. 1-8 ◽  
Author(s):  
Satyam Shukla ◽  
Sandeep Singh Gill ◽  
Navneet Kaur ◽  
H. S. Jatana ◽  
Varun Nehru
Keyword(s):  
Process Parameters ◽  
Simulation Analysis ◽  
Oxide Thickness ◽  
Channel Length ◽  
Deep Submicron ◽  
Device Structure ◽  
Short Channel ◽  
20 Nm ◽  
The Impact ◽  
Fin Shape

Technology scaling below 22 nm has brought several detrimental effects such as increased short channel effects (SCEs) and leakage currents. In deep submicron technology further scaling in gate length and oxide thickness can be achieved by changing the device structure of MOSFET. For 10–30 nm channel length multigate MOSFETs have been considered as most promising devices and FinFETs are the leading multigate MOSFET devices. Process parameters can be varied to obtain the desired performance of the FinFET device. In this paper, evaluation of on-off current ratio (Ion/Ioff), subthreshold swing (SS) and Drain Induced Barrier Lowering (DIBL) for different process parameters, that is, doping concentration (1015/cm3 to 1018/cm3), oxide thickness (0.5 nm and 1 nm), and fin height (10 nm to 40 nm), has been presented for 20 nm triangular FinFET device. Density gradient model used in design simulation incorporates the considerable quantum effects and provides more practical environment for device simulation. Simulation result shows that fin shape has great impact on FinFET performance and triangular fin shape leads to reduction in leakage current and SCEs. Comparative analysis of simulation results has been investigated to observe the impact of process parameters on the performance of designed FinFET.

Analytical and numerical study of the impact of HALOs on short channel and hot carrier effects in scaled MOSFETs

2002 ◽  
Vol 46 (3) ◽  
pp. 429-434 ◽  
Author(s):  
S. Zanchetta ◽  
A. Todon ◽  
A. Abramo ◽  
L. Selmi ◽  
E. Sangiorgi
Keyword(s):  
Numerical Study ◽  
Short Channel ◽  
Hot Carrier ◽  
Hot Carrier Effects ◽  
The Impact

Short-Channel Effects in 4H-SiC MOSFETs

2005 ◽  
Vol 483-485 ◽  
pp. 821-824
Author(s):  
Masato Noborio ◽  
Y. Kanzaki ◽  
Jun Suda ◽  
Tsunenobu Kimoto ◽  
Hiroyuki Matsunami
Keyword(s):  
Threshold Voltage ◽  
Empirical Relationship ◽  
Device Simulation ◽  
Oxide Thickness ◽  
Short Channel Effects ◽  
Short Channel ◽  
Channel Effects ◽  
Channel Lengths ◽  
P Type

Short-channel effects in SiC MOSFETs have been investigated. Planar MOSFETs with various channel lengths have been fabricated on p-type 4H-SiC (0001), (000-1) and (11-20) faces.^Short-channel effects such as punchthrough behavior, decrease of threshold voltage and deterioration of subthreshold characteristics are observed. Furthermore, the critical channel lengths below which short-channel effects occur are analyzed as a function of p-body doping and oxide thickness by using device simulation. The critical channel lengths in the fabricated SiC MOSFETs are in agreement with those obtained from the device simulation. The results are also in agreement with the empirical relationship for Si MOSFETs.

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