A manufacturable SOI CMOS process for low power digital, analog, and RF applications

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

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Low-Power Digital Part Design for a LF RFID tag in a Double-Poly 180 nm CMOS Process

2021 IEEE Conference of Russian Young Researchers in Electrical and Electronic Engineering (ElConRus) ◽

10.1109/elconrus51938.2021.9396585 ◽

2021 ◽

Author(s):

Kirill D. Liubavin ◽

Igor V. Ermakov ◽

Alexander Y. Losevskoy ◽

Andrey V. Nuykin ◽

Alexander S. Strakhov

Keyword(s):

Low Power ◽

Cmos Process ◽

Rfid Tag ◽

Digital Part

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An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽

10.3390/electronics10080889 ◽

2021 ◽

Vol 10 (8) ◽

pp. 889

Author(s):

Xiaoying Deng ◽

Peiqi Tan

Keyword(s):

Power Consumption ◽

Low Power ◽

Tuning Range ◽

Frequency Tuning ◽

Cmos Process ◽

Voltage Controlled Oscillator ◽

Back Gate ◽

Ultra Low Power ◽

Current Reuse ◽

K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

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A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽

10.3390/electronics10070805 ◽

2021 ◽

Vol 10 (7) ◽

pp. 805

Author(s):

Shi Zuo ◽

Jianzhong Zhao ◽

Yumei Zhou

Keyword(s):

Low Power ◽

Current Efficiency ◽

Phase Noise ◽

Duty Cycle ◽

Semiconductor Manufacturing ◽

Figure Of Merit ◽

Room Temperature ◽

Cmos Process ◽

Ultra Low Power ◽

Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

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