Low-Power Digital Part Design for a LF RFID tag in a Double-Poly 180 nm CMOS Process

2021 ◽  
Author(s):  
Kirill D. Liubavin ◽  
Igor V. Ermakov ◽  
Alexander Y. Losevskoy ◽  
Andrey V. Nuykin ◽  
Alexander S. Strakhov
Keyword(s):  
Low Power ◽  
Cmos Process ◽  
Rfid Tag ◽  
Digital Part

scholarly journals Low Power High-Efficiency Shift Register Using Implicit Pulse-Triggered Flip-Flop in 130 nm CMOS Process for a Cryptographic RFID Tag

Electronics ◽  
2016 ◽  
Vol 5 (4) ◽  
pp. 92 ◽  
Author(s):  
Mohammad Badal ◽  
Mamun Reaz ◽  
Zinah Jalil ◽  
Mohammad Bhuiyan
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Shift Register ◽  
Cmos Process ◽  
Flip Flop ◽  
Rfid Tag

scholarly journals Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

2019 ◽  
pp. 19-23
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Clock Signal ◽  
Voltage Level ◽  
Rfid Tag ◽  
Low Phase Noise

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

scholarly journals STUDY OF METHODS FOR REDUCING POWER CONSUMPTION AND AREA FOR A DIGITAL PART OF THE RFID-TAG

2020 ◽  
Author(s):  
Kirill Liubavin ◽  
Alexander Losevskoy ◽  
Igor Ermakov
Keyword(s):  
Power Consumption ◽  
Power Saving ◽  
Low Frequency ◽  
Reducing Power ◽  
Cmos Process ◽  
Rfid Tag ◽  
Dynamic Power ◽  
Digital Part ◽  
Cmos Processes

The results of the development of a digital part for the low-frequency RFID tag and the results of power saving methods study in 180 nm, 90 nm and 45 nm CMOS processes are presented. Using of the presented methods allows to reduce the power consumption and area of the digital part by 400 % and by 50 %, respectively. For the target 180 nm CMOS process the maximum dynamic power is less than 1 μW, and the occupied area is 0.042 mm2.

Design of a Novel Digital Baseband for UHF RFID Tag

2014 ◽  
Vol 513-517 ◽  
pp. 2938-2942
Author(s):  
Wei Lv ◽  
Xin An Wang ◽  
Ji Ting Su
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Peak Power ◽  
Cmos Process ◽  
Uhf Rfid ◽  
Power Module ◽  
Chip Area ◽  
Rfid Tag ◽  
Digital Baseband

This paper presents a novel low-power digital baseband for UHF RFID tag. The design is complied with a modified ISO 18000-6C protocol. In order to reduce the peak power, module-reuse and other advanced low power techniques are applied. And a novel baseband architecture is discussed, which fulfills the protocol functions and reduces power consumption. The whole tag chip, including digital baseband, RF/analog frontend and memory, has been taped out using TSMC 0.18um CMOS process. The chip area is 89234 um2 excluding test pads. Its power consumption is 11.63uw under 1.1v power supply.

An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder

2010 ◽  
Vol E93-C (6) ◽  
pp. 785-795
Author(s):  
Sung-Jin KIM ◽  
Minchang CHO ◽  
SeongHwan CHO
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
Rfid Tag ◽  
Front End

Analysis of 6T SRAM Cell in Different Technologies

2017 ◽  
Vol MCSP2017 (01) ◽  
pp. 7-10 ◽  
Author(s):  
Subhashree Rath ◽  
Siba Kumar Panda
Keyword(s):  
Low Power ◽  
Data Storage ◽  
Low Voltage ◽  
Random Access ◽  
Storage Device ◽  
Cmos Process ◽  
Process Technology ◽  
Digital Devices ◽  
Noise Margin ◽  
Sram Cell

Static random access memory (SRAM) is an important component of embedded cache memory of handheld digital devices. SRAM has become major data storage device due to its large storage density and less time to access. Exponential growth of low power digital devices has raised the demand of low voltage low power SRAM. This paper presents design and implementation of 6T SRAM cell in 180 nm, 90 nm and 45 nm standard CMOS process technology. The simulation has been done in Cadence Virtuoso environment. The performance analysis of SRAM cell has been evaluated in terms of delay, power and static noise margin (SNM).

scholarly journals An Ultra-Low-Power K-Band 22.2 GHz-to-26.9 GHz Current-Reuse VCO Using Dynamic Back-Gate-Biasing Technique

Electronics ◽  
2021 ◽  
Vol 10 (8) ◽  
pp. 889
Author(s):  
Xiaoying Deng ◽  
Peiqi Tan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Tuning Range ◽  
Frequency Tuning ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Back Gate ◽  
Ultra Low Power ◽  
Current Reuse ◽  
K Band

An ultra-low-power K-band LC-VCO (voltage-controlled oscillator) with a wide tuning range is proposed in this paper. Based on the current-reuse topology, a dynamic back-gate-biasing technique is utilized to reduce power consumption and increase tuning range. With this technique, small dimension cross-coupled pairs are allowed, reducing parasitic capacitors and power consumption. Implemented in SMIC 55 nm 1P7M CMOS process, the proposed VCO achieves a frequency tuning range of 19.1% from 22.2 GHz to 26.9 GHz, consuming only 1.9 mW–2.1 mW from 1.2 V supply and occupying a core area of 0.043 mm2. The phase noise ranges from −107.1 dBC/HZ to −101.9 dBc/Hz at 1 MHz offset over the whole tuning range, while the total harmonic distortion (THD) and output power achieve −40.6 dB and −2.9 dBm, respectively.

scholarly journals A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme

Electronics ◽  
2021 ◽  
Vol 10 (7) ◽  
pp. 805
Author(s):  
Shi Zuo ◽  
Jianzhong Zhao ◽  
Yumei Zhou
Keyword(s):  
Low Power ◽  
Current Efficiency ◽  
Phase Noise ◽  
Duty Cycle ◽  
Semiconductor Manufacturing ◽  
Figure Of Merit ◽  
Room Temperature ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Measured Phase

This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 μμW at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.

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