Analytical models of threshold voltage and breakdown voltage of short-channel MOSFET's derived from two-dimensional analysis

1979 ◽  
Vol 26 (4) ◽  
pp. 453-461 ◽  
Author(s):  
T. Toyabe ◽  
S. Asai
1999 ◽  
Vol 568 ◽  
Author(s):  
M.E. Rubin ◽  
S. Saha ◽  
J. Lutze ◽  
F. Nouri ◽  
G. Scott ◽  
...  

ABSTRACTExperiment shows that the reverse short channel effect (RSCE) in nMOS devices is critically impacted by the inclusion of nitrogen in the gate oxide. A higher concentration of nitrogen results in a lessened RSCE, i.e. more threshold voltage rolloff for smaller gate lengths. We propose that the additional nitrogen reduces the interstitial recombination rate at the interface, resulting in a smaller interstitial flux and therefore less transient enhanced diffusion (TED) of boron to that interface. To test this hypothesis, we simulate boron redistribution in one and two dimensional MOS capacitor structures, as well as full nMOS devices. We then present simulations calibrated to a 0.2 pim technology currently in production.


Author(s):  
Youssef Ahmed Mobarak ◽  
Moamen Atef

<span>The potential impact of high permittivity gate dielectrics on thin film transistors short channel and circuit performance has been studied using <a name="OLE_LINK110"></a><a name="OLE_LINK118"></a>highly accurate analytical models. In addition, the gate-to-channel capacitance and parasitic fringe capacitances have been extracted. The suggested model in this paper has been <a name="OLE_LINK37"></a><a name="OLE_LINK36"></a>increased the surface potential and decreased the <a name="OLE_LINK93"></a><a name="OLE_LINK92"></a>threshold voltage, whenever the conventional silicon dioxide gate dielectric<a name="OLE_LINK290"></a><a name="OLE_LINK280"></a> is replaced by high-K gate dielectric novel nanocomposite PVP/La<sub>2</sub>O<sub>3</sub>K<sub>ox</sub>=25. Also, it has been investigated that a decrease in parasitic outer fringe capacitance and gate-to-channel capacitance, whenever the conventional silicon nitride is replaced by low-K gate sidewall spacer dielectric novel nanocomposite PTFE/SiO<sub>2</sub>K<sub>sp</sub>=2.9. Finally, it has been demonstrated that using low-K gate sidewalls with high-K gate insulators can be decreased the gate fringing field and threshold voltage. In addition, fabrication of nanocomposites from polymers and nano-oxide particles found to have potential candidates for using it in a wide range of applications in low cost due to low process temperature of these nanocomposites materials.</span>


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