A Fully-Integrated 180 nm CMOS 1.2 V Low-Dropout Regulator for Low-Power Portable Applications

This paper presents the design and postlayout simulation results of a capacitor-less low dropout (LDO) regulator fully integrated in a low-cost standard 180 nm Complementary Metal-Oxide-Semiconductor (CMOS) technology which regulates the output voltage at 1.2 V from a 3.3 to 1.3 V battery over a –40 to 120°C temperature range. To meet with the constraints of system-on-chip (SoC) battery-operated devices, ultralow power (Iq = 8.6 µA) and minimum area consumption (0.109 mm2) are maintained, including a reference voltage Vref = 0.4 V. It uses a high-gain dynamically biased folded-based error amplifier topology optimized for low-voltage operation that achieves an enhanced regulation-fast transient performance trade-off.

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Design of Fully Integrated Impedimetric CMOS Biosensor for DNA Detection

Advanced Materials Research ◽

10.4028/www.scientific.net/amr.925.524 ◽

2014 ◽

Vol 925 ◽

pp. 524-528

Author(s):

Vinny Lam Siu Fan ◽

Yusmeeraz Binti Yusof

Keyword(s):

Dynamic Range ◽

Low Cost ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

High Gain ◽

Oxide Semiconductor ◽

Impedance Change ◽

Readout Circuit ◽

Label Free ◽

Fully Integrated

This paper described a label-free and fully integrated impedimetric biosensor using standard Complementary Metal Oxide Semiconductor (CMOS) technology to measure both capacitance and resistance of the electrode-electrolyte interface. Conventional impedance biosensors usually use bulky and expensive instruments to monitor the impedance change. This paper demonstrates a low power, high gain and low cost impedance readout circuit design for detecting the biomolecular interactions of deoxyribonucleic acid (DNA) strands at the electrode surface. The proposed biosensor circuit is composed of a transimpedance amplifier (TIA) with two quadrature phase mixers and finally integrated with 5μm x 5μm microelectrode based on 0.18μm Silterra CMOS technology process with 1.8V supply. The output value of the readout circuit is used to estimate the amplitude and phase of the measured admittance. The developed TIA can achieve a gain of 88.6dB up to a frequency of 50MHz. It also has very good linearity up to 2.7mA and the overall dynamic range is approximately 90dB.

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A Low-Voltage and Label-Free Impedance-Based Miniaturized CMOS Biosensor for DNA Detection

Jurnal Teknologi ◽

10.11113/jt.v67.2056 ◽

2014 ◽

Vol 67 (1) ◽

Author(s):

Vinny Lam Siu Fan ◽

Wong How Hwan ◽

Yusmeeraz Yusof

Keyword(s):

Dynamic Range ◽

Low Voltage ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Label Free ◽

Fully Integrated ◽

Technology Process ◽

Common Gate ◽

Study Designs

This study designs a low-voltage, label-free and fully integrated impedance-based biosensor using standard complementary metal oxide semiconductor (CMOS) technology to compute both capacitance and resistance of the electrode-electrolyte interface. The proposed biosensor circuit is composed of a common-gate transimpedance amplifier (CG-TIA) with two quadrature phase Gilbert cell double-balanced mixers and finally integrated with microelectrode using 0.18 µm Silterra CMOS technology process. The output value of the readout circuit was used to estimate the magnitude and phase of the measured admittance. The developed CG-TIA can achieve a gain of 88.6 dB up to a frequency of 50 MHz. The overall dynamic range was approximately 116 dB.

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Investigation of PVT-Aware STT-MRAM Sensing Circuits for Low-VDD Scenario

Micromachines ◽

10.3390/mi12050551 ◽

2021 ◽

Vol 12 (5) ◽

pp. 551

Author(s):

Zhongjian Bian ◽

Xiaofeng Hong ◽

Yanan Guo ◽

Lirida Naviner ◽

Wei Ge ◽

...

Keyword(s):

Nonvolatile Memory ◽

High Speed ◽

Low Voltage ◽

Supply Voltage ◽

Random Access ◽

Magnetic Tunnel Junction ◽

Complementary Metal Oxide Semiconductor ◽

Current Mode ◽

Cmos Technology ◽

Oxide Semiconductor

Spintronic based embedded magnetic random access memory (eMRAM) is becoming a foundry validated solution for the next-generation nonvolatile memory applications. The hybrid complementary metal-oxide-semiconductor (CMOS)/magnetic tunnel junction (MTJ) integration has been selected as a proper candidate for energy harvesting, area-constraint and energy-efficiency Internet of Things (IoT) systems-on-chips. Multi-VDD (low supply voltage) techniques were adopted to minimize energy dissipation in MRAM, at the cost of reduced writing/sensing speed and margin. Meanwhile, yield can be severely affected due to variations in process parameters. In this work, we conduct a thorough analysis of MRAM sensing margin and yield. We propose a current-mode sensing amplifier (CSA) named 1D high-sensing 1D margin, high 1D speed and 1D stability (HMSS-SA) with reconfigured reference path and pre-charge transistor. Process-voltage-temperature (PVT) aware analysis is performed based on an MTJ compact model and an industrial 28 nm CMOS technology, explicitly considering low-voltage (0.7 V), low tunneling magnetoresistance (TMR) (50%) and high temperature (85 °C) scenario as the worst sensing case. A case study takes a brief look at sensing circuits, which is applied to in-memory bit-wise computing. Simulation results indicate that the proposed high-sensing margin, high speed and stability sensing-sensing amplifier (HMSS-SA) achieves remarkable performance up to 2.5 GHz sensing frequency. At 0.65 V supply voltage, it can achieve 1 GHz operation frequency with only 0.3% failure rate.

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Photodetection Characteristics of Gold Coated AFM Tips and n-Silicon Substrate nano-Schottky Interfaces

Scientific Reports ◽

10.1038/s41598-019-49908-1 ◽

2019 ◽

Vol 9 (1) ◽

Cited By ~ 4

Author(s):

Yawar Abbas ◽

Ayman Rezk ◽

Fatmah Alkindi ◽

Irfan Saadat ◽

Ammar Nayfeh ◽

...

Keyword(s):

Low Cost ◽

Tunneling Current ◽

High Sensitivity ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Hot Electron ◽

Semiconductor Interface ◽

Afm Tips ◽

Tip Radius

Abstract Silicon (Si)-based photodetectors are appealing candidates due to their low cost and compatibility with the complementary metal oxide semiconductor (CMOS) technology. The nanoscale devices based on Si can contribute efficiently in the field of photodetectors. In this report, we investigate the photodetection capability of nano-Schottky junctions using gold (Au) coated conductive atomic force microscope (C-AFM) tips, and highly cleaned n-Si substrate interface. The Au nanotip/n-Si interface forms the proposed structure of a nano Schottky diode based photodetector. The electrical characteristics measured at the nanoscale junction with different Au nanotip radii show that the tunneling current increases with decreasing the tip radius. Moreover, the tunneling process and photodetection effects are discussed in terms of barrier width/height decrease at the tip-semiconductor interface due to the applied electric field as well as the generation of plasmon-induced hot-electron at the nanoparticle (i.e. C-AFM tip)/n-Si interface. Furthermore, the photodetection sensitivity is investigated and it is found to be higher for C-AFM tips with smaller radii. Moreover, this research will open a new path for the miniaturization of photodetectors with high sensitivity based on nano-Schottky interfaces.

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Complementary metal oxide semiconductor compatible high-voltage transistors

Canadian Journal of Physics ◽

10.1139/p87-161 ◽

1987 ◽

Vol 65 (8) ◽

pp. 1003-1008

Author(s):

P. Kempf ◽

R. Hadaway ◽

J. Kolk

Keyword(s):

Metal Oxide ◽

High Voltage ◽

Process Model ◽

Low Voltage ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Electrical Measurements ◽

Cmos Transistors

The purpose of this work was to study the implementation of high-voltage transistors using standard 3–5 μm complementary metal oxide semiconductor (CMOS) technology with a minimum of additional photolithographic or implant steps. A fabrication process was designed to accommodate a variety of high-voltage transistors with greater than 450 V breakdown voltage and low-voltage CMOS. Extensive use was made of a two-dimensional device model and a one-dimensional process model to determine suitable process parameters. The necessary conditions to produce a high-voltage double-diffused metal oxide semiconductor (DMOS) structure, as well as both n-well and p-well regions for CMOS transistors, and a thick gate oxide required to sustain the full blocking voltage were the main determinants of the process flow. Lateral DMOS (LDMOS), vertical DMOS (VDMOS), conductivity modulated FET (COMFET), and MOS triac (TRIMOS) devices were fabricated on the same chip as standard CMOS transistors using the developed fabrication sequence. This paper includes the results of the process modelling, device design, and electrical measurements.

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Fully Integrated Low-Ripple Switched-Capacitor DC–DC Converter with Parallel Low-Dropout Regulator

Electronics ◽

10.3390/electronics8010098 ◽

2019 ◽

Vol 8 (1) ◽

pp. 98 ◽

Cited By ~ 5

Author(s):

Jeong-Yun Lee ◽

Gwang-Sub Kim ◽

Kwang-Il Oh ◽

Donghyun Baek

Keyword(s):

Transient Response ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Switched Capacitor ◽

Wearable Electronics ◽

Power Sources ◽

Fully Integrated ◽

Fast Transient Response ◽

Low Dropout Regulator

In this paper, we propose a fully integrated switched-capacitor DC–DC converter with low ripple and fast transient response for portable low-power electronic devices. The proposed converter reduces the output ripple by filtering the control ripple via combining a low-dropout regulator with a main switched-capacitor DC–DC converter with a four-bit digital capacitance modulation control. In addition, the four-phase interleaved technique applied to the main converter reduces the switching ripple. The proposed converter provides an output voltage ranging from 1.2 to 1.5 V from a 3.3 V supply. Its peak efficiency reaches 73% with ripple voltages below 55 mV over the entire output power range. The transient response time for a load current variation from 100 μA to 50 mA is measured to be 800 ns. Importantly, the converter chip, which is fabricated using 0.13 μm complementary metal–oxide–semiconductor (CMOS) technology, has a size of 2.04 mm2. We believe that our approach can contribute to advancements in power sources for applications such as wearable electronics and the Internet of Things.

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Output Voltage Sampling Circuit for Discontinuous Conduction Mode Flyback Pulse-Width Modulation Controller

Journal of Circuits System and Computers ◽

10.1142/s0218126616501401 ◽

2016 ◽

Vol 25 (11) ◽

pp. 1650140 ◽

Cited By ~ 1

Author(s):

Ling-Feng Shi ◽

Zhen-Bo Shi ◽

Sen Chen ◽

Jian-Hui Xun

Keyword(s):

Pulse Width ◽

Output Voltage ◽

Pulse Width Modulation ◽

Low Voltage ◽

Low Cost ◽

Complementary Metal Oxide Semiconductor ◽

Oxide Semiconductor ◽

Cmos Process ◽

Discharge Time ◽

Constant Output

Primary-side controlled pulse-width modulation (PWM) flyback converter has been widely used in low-power and low-voltage products for its simple structure and low cost. This paper presents a novel output voltage sampling circuit which considers the influence of the rectifier diode current on the output voltage sampling. The output voltage sampling circuit samples the output voltage at 85% of the secondary inductance discharge time [Formula: see text] of last cycle, which improves the accuracy of the output voltage sampling circuit. Besides, the circuit can also sample the secondary inductance discharge time [Formula: see text]. Finally, a chip has been fabricated in 0.6[Formula: see text][Formula: see text]m complementary metal-oxide semiconductor (CMOS) process, which is used in the presented output voltage sampling circuit in its internal circuit to simple output voltage and achieve constant output voltage.

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Giant spin signals in chemically functionalized multiwall carbon nanotubes

Science Advances ◽

10.1126/sciadv.aba5494 ◽

2020 ◽

Vol 6 (31) ◽

pp. eaba5494

Author(s):

Roméo Bonnet ◽

Pascal Martin ◽

Stéphan Suffit ◽

Philippe Lafarge ◽

Aurélien Lherbier ◽

...

Keyword(s):

Low Voltage ◽

Hyperfine Interactions ◽

Multiwall Carbon Nanotubes ◽

Complementary Metal Oxide Semiconductor ◽

Cmos Technology ◽

Oxide Semiconductor ◽

Multiwall Carbon Nanotube ◽

Technology Roadmap ◽

Spin Polarized ◽

Multiwall Carbon

Transporting quantum information such as the spin information over micrometric or even millimetric distances is a strong requirement for the next-generation electronic circuits such as low-voltage spin-logic devices. This crucial step of transportation remains delicate in nontopologically protected systems because of the volatile nature of spin states. Here, a beneficial combination of different phenomena is used to approach this sought-after milestone for the beyond–Complementary Metal Oxide Semiconductor (CMOS) technology roadmap. First, a strongly spin-polarized charge current is injected using highly spin-polarized hybridized states emerging at the complex ferromagnetic metal/molecule interfaces. Second, the spin information is brought toward the conducting inner shells of a multiwall carbon nanotube used as a confined nanoguide benefiting from both weak spin-orbit and hyperfine interactions. The spin information is finally electrically converted because of a strong magnetoresistive effect. The experimental results are also supported by calculations qualitatively revealing exceptional spin transport properties of this system.

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Monolithically-Integrated Single-Photon Avalanche Diode in a Zero-Change Standard CMOS Process for Low-Cost and Low-Voltage LiDAR Application

Instruments ◽

10.3390/instruments3020033 ◽

2019 ◽

Vol 3 (2) ◽

pp. 33

Author(s):

Jinsoo Rhim ◽

Xiaoge Zeng ◽

Zhihong Huang ◽

Sai Rahul Chalamalasetti ◽

Marco Fiorentino ◽

...

Keyword(s):

Low Voltage ◽

Single Photon ◽

Low Cost ◽

Minimum Cost ◽

Complementary Metal Oxide Semiconductor ◽

Complete Characterization ◽

Oxide Semiconductor ◽

Cmos Process ◽

Avalanche Diode ◽

Monolithically Integrated

We present a single-photon sensor based on the single-photon avalanche diode (SPAD) that is suitable for low-cost and low-voltage light detection and ranging (LiDAR) applications. It is implemented in a zero-change standard 0.18-μm complementary metal oxide semiconductor process at the minimum cost by excluding any additional processing step for customized doping profiles. The SPAD is based on circular shaped P+/N-well junction of 8-μm diameter, and it achieves low breakdown voltage below 10 V so that the operation voltage of the single-photon sensor can be minimized. The quenching and reset circuit is integrated monolithically to capture photon-generated output pulses for measurement. A complete characterization of our single-photon sensor is provided.

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Design of Low Voltage Low Power High Gain Operational Transconductance Amplifier

U Porto Journal of Engineering ◽

10.24840/2183-6493_007.004_0008 ◽

2021 ◽

Vol 7 (4) ◽

pp. 103-110

Author(s):

Rajesh Durgam ◽

S. Tamil ◽

Nikhil Raj

Keyword(s):

Low Voltage ◽

Cmos Technology ◽

High Gain ◽

Floating Gate ◽

Operational Transconductance Amplifier ◽

Linear Mode ◽

Low Voltage Operation ◽

Transconductance Amplifier ◽

Amplifier Design ◽

Self Cascode

In this paper, a high gain structure of operational transconductance amplifier is presented. For low voltage operation with improved frequency response bulk driven quasi-floating gate MOSFET is used at the input. Further for achieving high gain the modified self cascode structure is used at the output. Compared to conventional self cascode the modified self cascode structure used provides higher transconductance which helps in significant boosting of gain of the amplifier. The modification is achieved by employing quasi-floating gate transistor which helps in scaling of the threshold which as a result increases the drain-to-source voltage of linear mode transistor thus changing it to saturation. This change of mode boosts the effective transconductance of self cascode MOSFET. The proposed operational transconductance amplifier when compared to its conventional showed improvement in DC gain by 30dB and also the unity gain bandwidth increases by 6 fold. The MOS models used for amplifier design are of 0.18µm CMOS technology at supply of 0.5V.

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