Compact Modeling of Drain Current in Double Gate Negative Capacitance MFIS Transistor

2018 ◽  
Author(s):  
Amol D. Gaidhane ◽  
Girish Pahwa ◽  
Amit Verma ◽  
Yogesh Singh Chauhan
Keyword(s):  
Drain Current ◽  
Compact Modeling ◽  
Negative Capacitance ◽  
Double Gate

Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

2021 ◽  
Author(s):  
SHIKHA U S ◽  
Rekha K James ◽  
Jobymol Jacob ◽  
Anju Pradeep
Keyword(s):  
Drain Current ◽  
Gate Oxide ◽  
Negative Capacitance ◽  
Double Gate ◽  
High K ◽  
Gate Control ◽  
Effect Transistor ◽  
Dimensional Simulation ◽  
The Impact ◽  
Low K

Abstract The drain current improvement in a Negative Capacitance Double Gate Tunnel Field Effect Transistor (NC-DG TFET) with the help of Heterojunction (HJ) at the source-channel region is proposed and modeled in this paper. The gate oxide of the proposed TFET is a stacked configuration of high-k over low-k to improve the gate control without any lattice mismatches. Tangent Line Approximation (TLA) method is used here to model the drain current accurately. The model is validated by incorporating two dimensional simulation of DG-HJ TFET with one dimensional Landau-Khalatnikov (LK) equation. The model matches excellently with the device simulation results. The impact of stacked gate oxide topology is also studied in this paper by comparing the characteristics with unstacked gate oxide. Voltage amplification factor (Av), which is an important parameter in NC devices is also analyzed.

Compact Modeling of Charge, Capacitance, and Drain Current in III–V Channel Double Gate FETs

2017 ◽  
Vol 16 (2) ◽  
pp. 347-354 ◽  
Author(s):  
Chandan Yadav ◽  
Mayank Agrawal ◽  
Amit Agarwal ◽  
Yogesh Singh Chauhan
Keyword(s):  
Drain Current ◽  
Compact Modeling ◽  
Double Gate ◽  
Charge Capacitance

scholarly journals Enhancement and Modeling of Drain Current in Negative Capacitance Double Gate TFET

Silicon ◽  
2021 ◽  
Author(s):  
Shikha U S ◽  
Rekha K James ◽  
Jobymol Jacob ◽  
Anju Pradeep
Keyword(s):  
Drain Current ◽  
Negative Capacitance ◽  
Double Gate

Compact Modeling of Lightly Doped Nanoscale DG MOSFET Transistor

2014 ◽  
Vol 492 ◽  
pp. 306-310
Author(s):  
Billel Smaani ◽  
Mourad Bella ◽  
Saϊda Latreche
Keyword(s):  
Dynamic Behavior ◽  
Drain Current ◽  
Compact Modeling ◽  
Double Gate ◽  
Static Behavior ◽  
Commercial Software ◽  
Dg Mosfet ◽  
Silvaco Atlas ◽  
Long Channel ◽  
First Time

In this paper, a compact modeling of lightly doped nanoscale Double Gate (DG) MOSFET transistor is presented. In the first time, a DG MOSFET transistor with long channel is considered. In this case, by using 1-D Poissons equation and applying the Gauss law at the interface of Silicone/Oxide, the static behavior of the long channel DG MOSFET can be observed by simple relationships between charges-voltages and charges-drain current. In second time, the dynamic behavior of the device is described through the intrinsic trans-capacitances. The present results (obtained using MATLAB) are validated by comparing them with those obtained using commercial software (Silvaco Atlas-TCAD).

Sign in / Sign up

Export Citation Format

Share Document