Electrical characterization and reliability investigations of Cu TSVs with wafer-level Cu/Sn-BCB hybrid bonding

2012 ◽  
Author(s):  
Y. J. Chang ◽  
C. T. Ko ◽  
Z. C. Hsiao ◽  
T. H. Yu ◽  
Y. H. Chen ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Wafer Level

In FAB 300mm Wafer Level Atomic Force Probe Characterization

2012 ◽  
Author(s):  
Terence Kane
Keyword(s):  
Electrical Characterization ◽  
Dark Field ◽  
Wafer Level ◽  
Electrical Measurements ◽  
Manufacturing Line ◽  
Atomic Force ◽  
Monitoring Tools ◽  
Voltage Contrast ◽  
The Cost ◽  
Non Destructive

Abstract A 300mm wafer atomic force prober (AFP) has been installed into IBM’s manufacturing line to enable rapid, nondestructive electrical identification of defects. Prior to this tool many of these defects could not detected until weeks or months later. Moving failure analysis to the FAB provides a means of complementing existing FAB inspection and defect review tools as well as providing independent, non-destructive electrical measurements at an early point in the manufacturing cycle [1] Once the wafer sites are non destructively AFP characterized, the wafer is returned to its front opening unified pod (FOUP) carrier and may be reintroduced into the manufacturing line without disruption for further inspection or processing. Whole wafer atomic force probe electrical characterization has been applied to 32nm, 28nm, 20nm and 14nm node technologies. In this paper we explore the cost benefits of performing non-destructive AFP measurements on whole wafers. We have found the methodology of employing a whole wafer AFP tool complements existing in-line manufacturing monitoring tools such as brightfield/dark field optical inspection, SEM in-line inspection and in-line E-beam voltage contrast inspection (EBI).

Electrical Characterization on a High-Speed Wafer-Level Package

2013 ◽  
Vol 2013 (DPC) ◽  
pp. 001937-001962
Author(s):  
Kai Liu ◽  
YongTaek Lee ◽  
HyunTai Kim ◽  
MaPhooPwint Hlaing ◽  
Susan Park ◽  
...  
Keyword(s):  
High Speed ◽  
Unit Length ◽  
Ground Plane ◽  
Measurement Data ◽  
Electrical Characterization ◽  
Electrical Performance ◽  
Metal Loss ◽  
Signal Loss ◽  
Wafer Level ◽  
Wafer Level Package

In this paper, a 2-layer eWLB (embedded Wafer-Level BGA) is studied and its performance is compared with an equivalent 4-layer laminate package. Since eWLB package is processed by using lithographical method, design rules on width (W) and spacing (S) are much finer (usually 2–3 times finer) than those for laminate package. In other words, signal traces can be implemented in smaller fan-out regions. The smaller feature sizes for signal traces would end up with more metal loss per unit length. But as the signal traces can be implemented in smaller fan-out regions, overall trace-routing may be shorter, and equivalent insertion-loss may be achieved. In eWLB, the ground plane is closer to the signal traces. This actually helps to reduce cross-talk between wide I/O buses, as the electrical field is contained in a smaller region by the closer ground plane. Another key advantage from wafer-level package is a smoother metal surface, which greatly reduces the extra signal loss, due to surface-roughness effect, especially for higher-frequency and higher-speed applications. In addition, through-via structures for wafer-level package are typically 2–3 times smaller. This allows to implement power/ground planes in a more continuous way, achieving better resistance and inductance for power/ground nets. Overall electrical performance, which takes into account of all the impacts above, can be evaluated by signal-integrity analysis (E-diagram). Measurement data of a 2-layer eWLB package for a LPDDR application will be presented, which shows the comparable performance typically obtained from a 4-layer laminate package

3D RCP Package Stacking: Side Connect, An Emerging Technology for System Integration and Volumetric Efficiency

2013 ◽  
Vol 2013 (1) ◽  
pp. 000447-000451 ◽  
Author(s):  
Michael Vincent ◽  
Doug Mitchell ◽  
Jason Wright ◽  
Yap Weng Foong ◽  
Alan Magnus ◽  
...  
Keyword(s):  
System Integration ◽  
System Performance ◽  
Electrical Characterization ◽  
Emerging Technology ◽  
Volumetric Efficiency ◽  
Wafer Level ◽  
Novel Technologies ◽  
3D Packaging ◽  
Packaging Space ◽  
On Chip

Fan-out wafer level packaging (FO-WLP) has shifted from standard single die, single sided package to more advanced packages for System-in-Package (SiP) and 3D applications. Freescale's FO-WLP, Redistributed Chip Package (RCP), has enabled Freescale to create novel SiP solutions not possible in more traditional packaging technologies or Systems-on-Chip (SoC). Simple SiP's using two dimensional (2D), multi-die RCP solutions have resulted in significant package size reduction and improved system performance through shortened traces when compared to discretely packaged die or substrate based multi-chip module (MCM). More complex 3D SiP solutions allow for even greater volumetric efficiency of the packaging space. 3D RCP is a flexible approach to 3D packaging with complexity ranging from Package-on-Package (PoP) type solutions to systems including ten or more multi-sourced die with associated peripheral components. Perhaps the most significant SiP capability of the RCP technology is the opportunity for heterogeneous integration. The combination of various system elements including, but not limited to SMD's, CMOS, GaAs, MEMS, imaging sensors or IPD's gives system designers the capability to generate novel systems and solutions which can then enable new products for customers. To enable this ever increasing system integration and volumetric efficiency, novel technologies have been developed to utilize the full package space. Technologies such as through package via (TPV) and double sided redistribution are currently proving successful. For this discussion, an emerging technology for 3D RCP package stacking that can further enhance design flexibility and system performance is presented. This technology, package side connect, utilizes the vertical sides of packages and stacked packages to capture a normally unused piece of package real-estate. Mechanical and electrical characterization of successful side connects will be presented as well as reliability results of test vehicle packages using RCP packaging technology.

Design and electrical characterization of wafer-level micro-package for GaAs-based RFMEMS switches

2013 ◽  
Vol 59 (3) ◽  
pp. 201 ◽  
Author(s):  
Sandeep Chaturvedi ◽  
GSai Saravanan ◽  
MahadevaK Bhat ◽  
R Muralidharan ◽  
ShibanK Koul ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Wafer Level

Advanced 3D eWLB-SiP (embedded Wafer Level Ball Grid Array – System in Package) Technology

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-20
Author(s):  
Seung Wook Yoon
Keyword(s):  
Form Factor ◽  
Power Efficiency ◽  
High Performance ◽  
Electrical Characterization ◽  
Cost Effective ◽  
Electrical Performance ◽  
Wearable Electronics ◽  
Wafer Level ◽  
Low Profile ◽  
Line Spacing

FO-WLP (Fan-Out Wafer Level Packaging) has been established as one of the most versatile packaging technologies in the recent past and is already accounting for a market value of over 1 billion USD due to its unique advantages. The technology combines high performance, increased functionality with a high potential for heterogeneous integration and reduce the total form factor as well as cost-effectiveness. The emerging of advanced of silicon node technology down to 10 nanometer (nm) in support of higher performance, bandwidth and better power efficiency in mobile products pushes the boundaries of emerging packaging technologies to smaller form-factor packaging designs with finer line/spacing as well as improved thermal electrical/performance and integration of SiP or 3D capabilities. Advanced eWLB FO-WLP technology provides a versatile platform for the semiconductor industry's technology evolution from single or multi-die 2D package designs to 2.5D interposers and 3D System-in-Package (SiP) configurations. This paper reports developments that extend multi-die and 3D SiP applications with eWLB technology, including ultra thin devices or/and with an interposer substrate attachment. Test vehicles have been designed and fabricated to demonstrate and characterize integrated packaging solutions for network, mobile products including IoT and wearable electronics. The test vehicles have ranged from ~30mm2 to large sizes up to ~230mm2 and 0.4mm ball pitch. Assembly process details including 3D vertical interconnect, laser ablation, RDL processes and mechanical reliability characterizations are to be discussed with component and board level reliability results. In addition, warpage behavior and the PoP stacking process will also be presented. Innovative structure optimization that provides dual advantages of both height reduction and enhanced package reliability are reported. To enable higher interconnection density and signal routing, packages with multiple redistribution layers (RDL) and fine line/width spacing are fabricated and implemented on the eWLB platform. Successful reliability and electrical characterization results on multi-die and 3D eWLB-SiP configurations are reported as an enabling technology for highly integrated, miniaturized, low profile and cost effective solutions.

Mechanical and Electrical Characterization of an IC Bond Pad Stack Using a Novel In-Situ Methodology

2003 ◽  
Author(s):  
C.D. Hartfield ◽  
J.J. Broz ◽  
T.M. Moore
Keyword(s):  
Integrated Circuit ◽  
Electrical Characterization ◽  
Dynamic Contact ◽  
Wafer Level ◽  
New Class ◽  
Increased Risk ◽  
Bond Pads ◽  
Low K

Abstract The semiconductor industry’s efforts to integrate dielectrics into Si devices has driven characterization efforts to address the challenges presented by adoption of this new class of materials. Abundant literature exists on the considerations required for CMP process recommendations for successful fabrication, adhesion requirements for both fabrication and assembly, and considerations for interconnect structure to enable wire-bonding. There is also interest in understanding the wafer level test challenges presented by the low-K devices. In addition to the typical concerns about reaching the best compromise of good contact resistance (CRES) performance with a minimum amount of probe damage, low-K materials present an increased risk of compromising the dielectric or barrier layers beneath bond pads. For a better understanding of the dynamic contact phenomenon of probing and its effect on the integrated circuit (IC) metal stack, a specialized in-situ nanomanipulator tool was developed for simultaneous visualization of probing events with data recording of electrical and load measurements. This paper describes initial research with this new tool.

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