Parametric Studies for Thermal Design of Surface Mounted Components of Standard Electronic Modules

1992 ◽  
Vol 114 (3) ◽  
pp. 300-304 ◽  
Author(s):  
A. Hadim ◽  
N. J. Nagurny

Parametric studies are performed on heat transfer in surface-mounted components of conduction cooled Standard Electronic Modules (SEMs). Thermal network models are developed for the various components that are used in the SEMs. The models are validated by comparing the results with available experimental results from various test modules. An interfacing software package for thermal analysis (IN-STAN) is used to generate the thermal network representations of the models and a thermal network analyzer is used to perform the analysis. Several studies are performed to analyze the effects of important thermal design parameters including: chip and carrier size, cavity floor thickness, air gap thickness, die and carrier materials, and solder material.

2019 ◽  
Vol 191 ◽  
pp. 200-210 ◽  
Author(s):  
O.M. Brastein ◽  
B. Lie ◽  
R. Sharma ◽  
N.-O. Skeie

Author(s):  
Koji Nishi ◽  
Tomoyuki Hatakeyama ◽  
Shinji Nakagawa ◽  
Masaru Ishizuka

The thermal network method has a long history with thermal design of electronic equipment. In particular, a one-dimensional thermal network is useful to know the temperature and heat transfer rate along each heat transfer path. It also saves computation time and/or computation resources to obtain target temperature. However, unlike three-dimensional thermal simulation with fine pitch grids and a three-dimensional thermal network with sufficient numbers of nodes, a traditional one-dimensional thermal network cannot predict the temperature of a microprocessor silicon die hot spot with sufficient accuracy in a three-dimensional domain analysis. Therefore, this paper introduces a one-dimensional thermal network with average temperature nodes. Thermal resistance values need to be obtained to calculate target temperature in a thermal network. For this purpose, thermal resistance calculation methodology with simplified boundary conditions, which calculates thermal resistance values from an analytical solution, is also introduced in this paper. The effectiveness of the methodology is explored with a simple model of the microprocessor system. The calculated result by the methodology is compared to a three-dimensional heat conduction simulation result. It is found that the introduced technique matches the three-dimensional heat conduction simulation result well.


2012 ◽  
Vol 20 (6) ◽  
pp. 1208-1217
Author(s):  
郭亮 GUO Liang ◽  
吴清文 WU Qing-wen ◽  
颜昌翔 YAN Chang-xiang

2017 ◽  
Vol 27 (4) ◽  
pp. 1-5 ◽  
Author(s):  
Shiva Charan Indrakanti ◽  
Jin-Geun Kim ◽  
Chul H. Kim ◽  
Sastry V. Pamidi

Author(s):  
Masaru Ishizuka ◽  
Shinji Nakagawa ◽  
Katsuhiro Koizumi

Thermal design is one of the most important issues in the development of compact self—ballasted fluorescent lamps as the demand for small yet powerful lamps is mounting. This paper proposes a simulation method that is based on a thermal network model for which a set of equations are developed. Some of the coefficients of the thermal network equations were determined experimentally using a simulated model lamp. The calculated temperatures are in good agreement with the measured temperatures. The work illustrates the usefulness of the proposed methodology in the design of compact self—ballasted fluorescent lamps.


Author(s):  
Harita Machiraju ◽  
Bill Infantolino ◽  
Bahgat Sammakia ◽  
Michael Deeds

A MEMS based device consisting of microactuators was modeled using finite element analysis. The temperature profile of the complete package was obtained and compared to experimental measurements. Good agreement was found between the modeling and measurements. Parametric studies of potential design parameters of the chip package to decrease the power requirements to the actuators have been studied. Increasing the gap between the handle layer and the device layer of the SOI (silicon on insulator) chip from 2 to 3 microns resulted in a reduction of 10% (0.2 Watts) per beam of the actuator. A glass top chip proved to be better at reducing the power requirements for the actuators when compared to a silicon top chip. Modeling shows that relief cuts in the substrate had a larger effect on the power reduction compared to those on the top chip since the heat conduction path to the substrate is a lower resistance path. The power reduction was as high as 50% (1.1 Watts) per beam of the actuator, when the relief cut in the substrate was 50 microns.


Author(s):  
Kenneth C. Walls ◽  
David L. Littlefield ◽  
David E. Lambert

In order to make the process of fragmentation of warhead cases more systematic, we have developed a procedure that makes use of nonlinear optimization to derive optimal values for case design parameters subject to various design constraints. A framework has been developed that makes use of the optimization software package LS-OPT driving the hydrocode CTH (CTH is developed and maintained at Sandia National Laboratories, LS-OPT is commercially available from Livermore Software Technology Corp.). CTH was used to model the explosive detonation and determine the resultant kinetic energy delivered to the case by the energetic material. As an example of application of the framework, a test problem was run using a case configuration consisting alternating titanium alloy and polymer layers.


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