Fatigue Prediction for Molded Wafer-Level Package During Temperature Cycling

2019 ◽  
Vol 142 (1) ◽  
Author(s):  
Wan-Chun Chuang ◽  
Wei-Long Chen

Abstract A molded wafer-level package simulation model was successfully developed for calculating solder ball fatigue life during a temperature cycle test (TCT), revealing that the most crucial factor affecting fatigue life, rather than being the maximal stress in solder balls, is the equivalent strain range in solder balls during the creep effect. Accordingly, in a TCT, the fatigue life of the solder balls, which are located from the outer edge to the center, is negatively correlated with the equivalent strain range; the earliest solder balls to rupture are those located at the outer edges, which have the highest equivalent strain range but not the highest stress. Regarding the fatigue life distribution, the simulation results differed from the experiment results by only 6.4%. Additionally, the effects of mold compound protection type and thickness on fatigue life were investigated. When the thickness was changed from 85 to 25 μm, the solder ball fatigue life increased to approximately 1230 cycles, which satisfies the production standard of 500 cycles and is 1.86 times longer than the fatigue life in the existing production line. Reduction in mold compound thickness reduced the amount of material required to 29% of that in the current production line. The model established in this study is expected to be applied in future integrated circuit package design for product reliability.

Author(s):  
Charles R. Krouse ◽  
Grant O. Musgrove ◽  
Taewoan Kim ◽  
Seungmin Lee ◽  
Muhyoung Lee

Abstract When considering mechanical components that are subjected to complex loading conditions, it is difficult to achieve accurate predictions of low-cycle fatigue life. For multiaxial and non-proportional loads, the principal strain directions vary in three-dimensional space with time. The commonly accepted methods to determine fatigue life under such loading conditions are based on a critical plane approach, and they rely heavily on accurate strain range estimates. However, there is no singly accepted method to determine the critical plane, equivalent strain magnitude, or equivalent strain direction. Furthermore, current suggestions are computationally intensive and challenging to implement. This paper offers a novel and concise method to accurately determine equivalent strain range and equivalent strain direction under multiaxial, non-proportional loading in three-dimensional space. A practical approach is provided for implementing the method, and an example of an application using a finite element model of a first stage turbine blade is discussed. To demonstrate the approach, ANSYS Mechanical was used to simulate a turbine blade under transient loading conditions and to determine the resulting strains. Equivalent strain range results were applied to a Coffin-Manson relation to determine the low-cycle fatigue life of every node within the finite element model of the first stage turbine blade. The post-processing of the strain predictions, which yielded the equivalent strain range and equivalent strain direction, is discussed in detail.


2011 ◽  
Vol 361-363 ◽  
pp. 1669-1672
Author(s):  
Wen Xiao Zhang ◽  
Guo Dong Gao ◽  
Guang Yu Mu

The low cycle fatigue behavior was experimentally studied with the 3-dimension notched LD8 aluminum alloy specimens at 300°C. The 3- dimension stress-strain responses of specimens were calculated by means of the program ADINA. The multiaxial fatigue life prediction was carried out according to von Mises’s equivalent theory. The results from the prediction showed that the equivalent strain range can be served as the valid mechanics for predicting multiaxial high temperature and low cyclic fatigue life.


1999 ◽  
Vol 121 (1) ◽  
pp. 18-22 ◽  
Author(s):  
B. Nagaraj

Over molded pad array carrier (OMPAC) also called as ball grid array (BGA) has been used in products, such as hand held two way radio within Motorola. Now it has gained interest outside Motorola in companies like Compaq for portable computers and AT&T for the telephone systems. The reduced size, thickness, and increased I/O density at the board level are the attractive features of the OMPAC package over other competing package types. In Ref. [1, 2], life time of C5 solder interconnects under temperature cycle loading was reported. That study was based on nonlinear FEM simulation incorporating creep behavior of the solder. In the current study, influence of four key package design variables on C5 solder reliability is addressed using analyses methodology described in Ref. [1, 2]. The selected design variables are thickness of the substrate, the C5 pitch, solder ball diameter, and height to diameter (h/d) ratio of the C5 interconnect. For each design variable, three levels (low, middle, and high) are considered. The full study required a total of 81 simulation runs. However, statistical design of experiments were used and an L9 design was selected in the current study. The maximum permanent strain range for stabilized temperature cycle was calculated for all the nine case studies. In all the cases it occurs at the substrate interface in the solder ball just inside the edge of the die. The response (maximum total permanent strain range and thus maximum number of temperature cycles before failure) as a function of the four design variables are studied and the trends are: as the substrate thickness, C5 ball diameter and C5 (h/d) ratio increases and C5 pitch decreases, the maximum total permanent strain range decreases and thus cycles to failure increases. The order of importance of the design variables for the C5 reliability are (i) the C5 (h/d) ratio, (ii) the C5 ball diameter, (iii) the C5 pitch, and (iv) the substrate thickness. The C5 (h/d) is the key design variable. The maximum total permanent strain range decreases from 0.0055 for (h/d) ratio of 0.5 to 0.0045 for (h/d) ratio of 0.7. This in other words increases cycles to failure from 3000 cycles to 4400 cycles, an improvement of 47 percent.


2016 ◽  
Vol 2016 (1) ◽  
pp. 000410-000414 ◽  
Author(s):  
Amit Kelkar ◽  
Vivek Sridharan ◽  
Khanh Tran ◽  
Kiyoko Ikeuchi ◽  
Anu Srivastava ◽  
...  

Abstract The ever increasing demand for high levels of integration and miniaturization has created new transistor nodes, shrunk redistribution line width/space, and driven a reduction in solder bump pitch. This has created the need for Fan-out packaging. This paper presents a novel Fan-out Wafer level package which does not require use of molding process or materials used typically in such packages. In this technique, silicon is used as the carrier material instead of molding compound. Advantages of silicon include good reliability, high thermal stability, and low cost. This novel Mold-free Fan-out package passes standard reliability tests including temperature cycling (TCT), Drop test (DT), and Convection reflow.


2011 ◽  
Vol 2011 (1) ◽  
pp. 000953-000960 ◽  
Author(s):  
Thomas Oppert ◽  
Rainer Dohle ◽  
Jörg Franke ◽  
Stefan Härter

The most important technology driver in the electronics industry is miniaturization mainly driven by size reduction on wafer level and cost. One of the interconnection technologies for fine pitch applications with the potential for highest integration and cost savings is Flip Chip technology. The commonly used method of generating fine pitch solder bumps is by electroplating the solder. This process is difficult to control or even impossible if it comes to ternary or quaternary alloys. The work described in this study addresses the limitations of existing bumping technologies by enabling low-cost, fine pitch bumping and the use of a very large variety of solder alloys. This flexibility in the selection of the solder materials and UBM stacks is a large advantage if it is essential to improve temperature cycling resistance, drop test resistance, or to increase electromigration lifetime. The technology allows rapid changeover between different low melting solder alloys. Tighter bump pitches and a better bump quality (no flux entrapment) are achievable than with screen printing of solder paste. Because no solder material is wasted, the material costs for precious metal alloys like Au80Sn20 are much lower than with other bumping processes. Solder bumps with a diameter between to date 30 μm and 500 μm as well as small and large batches can be manufactured with one cost efficient process. To explore this potential, cost-efficient solder bumping and automated assembly technologies for the processing of Flip Chips have been developed and qualified. Flip Chips used in this study are 10 mm by 10 mm in size, have a pitch of 100 μm and a solder ball diameter of 30 μm, 40 μm or 50μm, respectively. Wafer level solder application has been done using wafer level solder sphere transfer process or solder sphere jetting technology, respectively. The latter tool has been used for many years in the wafer level packaging industry for both Flip Chip and chip scale packaging applications. It is commonly known in the industry as a solder ball bumping equipment. For the described work the process was scaled down for processing solder spheres with a diameter of 30 μm what was never done before that way worldwide. The research has shown that the underfill process is one of the most crucial factors when it comes to Flip Chip miniaturization for high reliability applications. Therefore, high performance underfill material was qualified initially [1]. Final long term reliability testing has been done according to MIL-STD883G, method 1010.8, condition B up to thirteen thousand cycles with excellent performance of the highly miniaturized solder joints. SEM/EDX and other analysis techniques will be presented. Additionally, an analysis of the failure mechanism will be given and recommendations for key applications and further miniaturization will be outlined.


1998 ◽  
Vol 120 (3) ◽  
pp. 290-295 ◽  
Author(s):  
B. Nagaraj ◽  
M. Mahalingam

Over molded pad array carrier (OMPAC), also called plastic Ball Grid Array (pBGA) package family offers increased I/O density at the board level; further, package size and thickness are reduced in comparison to other competing package types leading to many product applications. The OMPAC package is investigated for solder pad interconnect reliability. Elastic and inelastic finite element method (FEM) simulations are employed with experimental temperature cycling data. Linear elastic analyses are performed for various package parameters that influence the stress distribution in the solder pad interconnect for temperature loading. The package parameters considered are (a) ratio of thickness of die to substrate (tdie/tsub.), (b) ratio of width of die to substrate (wdie/wsub.), and (c) ratio of height to diameter of the solder pad interconnect ((h/d)pad). The results are evaluated based on the maximum Tresca (maximum shear stress) failure criterion. The key parameter is (h/d)pad ratio. As this ratio increases, the maximum Tresca failure criterion decreases. The performance of the solder pads are evaluated based on the maximum total permanent strain (plastic + creep) range per temperature cycle. FEM simulation was performed up to eight consecutive temperature cycles. The permanent strain (plastic + creep) range were calculated for each temperature cycle and observed that after a few temperature cycles the strain ranges stabilize. The maximum stabilized total permanent strain range is in the inner solder pad and is equal to 0.005. This maximum total strain range in the solder pad per temperature cycle loading can be used to estimate the life time of the solder pads. The FEM simulation results are correlated with the experimental data. Both the simulation and the experimental results are indicate that the outer pads are not as critical as the inner or the middle pads. The experimental results indicate that there is slightly larger probability for the middle pads to fail before the inner pads. However, the simulation data indicate that the inner pads are more critical than the middle pads. We believe that this small discrepancy in simulation result is due to the actual temperature variation on the package not being included in the present analysis.


2012 ◽  
Vol 28 (1) ◽  
pp. 135-142 ◽  
Author(s):  
R.-S. Chen ◽  
C.-H. Huang ◽  
Y.-Z. Xie

ABSTRACTThis paper deals with the optimal design for a twin die stacked package. Firstly, the numerical model is built up in terms of a three-dimensional slice model along the diagonal direction of the package. The material behavior of the solder balls is a consequence of the viscoplastic property which can be described by the Anand's model. Secondly, the Darveaux model is applied to predict the solder ball reliability of the stacked die package under a cyclic temperature loading. Since simulation analysis found an obvious relation is found between the fatigue life of the solder ball and the distribution of the accumulated strain energy density (SED) on the critical solder ball of the package through the simulation analysis, the average value of the strain energy density for all solder balls is adopted as the optimization indicator of reliability. With such a viewpoint, the critical solder ball position can be ignored, and accordingly an efficient analysis can be obtained. Finally, the Box-Behnken regression model is adopted to construct all the experiments. Each experiment analyzes the reliability of the package under varying parameters. Subsequently, the pattern search algorithm is applied to search for optimal factors.Through optimal analysis with the fatigue reliability indicator of an average SED, the fatigue life is found to be 59% lower than that of the original design. The fatigue life had clearly improved and the lowest ball fatigue life is found to be 2.859 times longer than the original one.


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