A Packaging Solution for Pressure Sensor MEMS

In this paper, a wafer-level packaging solution for pressure sensor microelectromechanical system (MEMS) is reported. Sensor and glass cap wafers are anodically bonded at a bonding temperature less than 400°C. Bubble free interfaces are obtained and the bond strength is higher than 20 MPa. Sensor and bottom silicon cap wafers are bonded at a temperature of 400–450°C with the assistance of a gold intermediate layer. The bond strenght is higher than 5 MPa. The via holes, used for feedthroughs leading out the circuit, on bottom silicon cap wafer are anisotropically formed in KOH etching solution. Aluminum layer is sputtered on the bottom silicon wafer for electrical connection, re-routing circuit and the seed layer of under bump metallization (UBM). During sputtering process, the sidewalls of via holes are also sputtered with aluminum film. At the same time, the metal pads on sensor wafer are also built up to connect with metallized via holes. It is found that the cavities are vacuum sealed. Sputtered Cr/Ni/Au layers are used for UBM layers. Finally, solder bumps can printed or plated on the UBM. The whole process leads to promising performance of the devices.

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Wafer Level Packaging of RF MEMS for Flip Chip Assembly

Electronic and Photonic Packaging, Electrical Systems and Photonic Design, and Nanotechnology ◽

10.1115/imece2003-42825 ◽

2003 ◽

Author(s):

J. Wei ◽

B. K. Lok ◽

P. C. Lim ◽

M. L. Nai ◽

H. J. Lu ◽

...

Keyword(s):

Flip Chip ◽

Rf Mems ◽

Bonding Temperature ◽

Etching Process ◽

Glass Wafer ◽

Wafer Level ◽

Pressure Balance ◽

Etching Depth ◽

Wafer Level Packaging ◽

Via Holes

In this paper, the development of wafer level packaging of radio frequency (RF) microelectromechanical system (MEMS) is reported. The packaging process consists of wafer bonding, wafer thinning, via etching, plating, under-bump-metallization (UBM) and bumping processes. 6-inch Si and glass wafers are used in the study. RF MEMS devices are fabricated on Si wafers and sandwiched between Si and glass cap wafers. To maintain the pressure balance between the cavities and outside world after bonding process, Si and glass wafers are anodically bonded at a pressure of 2 bar and a bonding temperature of 400 °C. The cavities are hermetically sealed. The glass wafer of the bonded pair is thinned down to 100 μm using mechanical polishing and chemical etching, the good uniformity of the wafer thickness is maintained with etching process. A layer of Cr/Au is sputtered and patterned as the hard mask for glass via etching process. Via holes with undercut closer to the etching depth are formed in HF+HNO3 acid. After stripping the metal mask, a seed layer of TiW/Cu is deposited using sputtering and plating processes. TiW layer is used to enhance the adhesion of metal and glass. With the completion of the re-routing and via metallization processes, benzocyclobutene (BCB) photoresist is used to planarize via holes and opened for UBM process. Finally, the packaged devices can be assembled using flip chip approach.

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Wafer Level Chip Size Packaging Technology for Bulk Acoustic Wave Filters

MRS Proceedings ◽

10.1557/proc-0990-b07-14 ◽

2007 ◽

Vol 990 ◽

Author(s):

Hajime Yamada ◽

Naoko Aizawa ◽

Hiroyuki Fujino ◽

Yoshihiro Koshido ◽

Yukio Yoshino

Keyword(s):

Acoustic Wave ◽

Flip Chip ◽

Bulk Acoustic Wave ◽

Wafer Level ◽

Copper Electroplating ◽

Solder Bumps ◽

Hermetic Seal ◽

Via Holes ◽

Chip Size ◽

Wave Filters

ABSTRACTWafer level chip size packages (WL-CSP) have been successfully fabricated for bulk acoustic wave (BAW) filters. WL-CSP has been completed at the wafer level prior to dicing. Two silicon wafers are used as a die and a lid for chip size packaging. Both device and lid wafers have the same expansion coefficient and the package is strong enough to withstand the thermal stress. The package has a hermetic seal with copper-tin intermetallic bonding. The bonded wafers are then thinned by grinding. Via holes are formed by reactive ion etching (RIE) and filled by copper electroplating. The package has solder bumps on each terminal, ready for flip-chip assembly. We have succeeded to produce CSP-BAW filters with a hermetically sealed cavity, which is 840 micrometers squared and 280 micrometers in height including solder bumps.

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Design and Fabrication of WLP Compatible Miniaturized Pressure Sensor System with Through Silicon Via (TSV) Interconnects

International Symposium on Microelectronics ◽

10.4071/isom-2011-ta1-paper5 ◽

2011 ◽

Vol 2011 (1) ◽

pp. 000033-000043 ◽

Cited By ~ 1

Author(s):

Tao WANG ◽

Jian CAI ◽

Qian WANG ◽

Hao ZHANG ◽

Zheyao WANG

Keyword(s):

Pressure Sensor ◽

Flip Chip ◽

Electrical Signal ◽

Sensor System ◽

Wafer Level ◽

Through Silicon Via ◽

Bonding Structure ◽

Wafer Level Packaging ◽

Piezoresistive Pressure Sensor ◽

Processing Circuit

In this paper, a Wafer Level Packaging (WLP) compatible pressure sensor system enabled with Through Silicon Via (TSV) and Au-Sn inter-chip micro-bump bonding is designed and fabricated in lab, in which TSV transmits electrical signal from piezoresistive circuit to processing circuit vertically. The pressure sensor system includes TSV integrated piezoresistive pressure sensor chip and Read-Out Integrated Chip (ROIC) in which TSV also incorporated. Two CMOS compatible fabrication process flows for pressure sensor system are demonstrated. And, flip chip bonding structure of TSV integrated pressure sensor with a ROIC are realized using one of these two process flows. Inter-chip interconnects enabled with TSV and micro-bump bonding is obtained.

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