Wafer Level Packaging of RF MEMS for Flip Chip Assembly

2003 ◽  
Author(s):  
J. Wei ◽  
B. K. Lok ◽  
P. C. Lim ◽  
M. L. Nai ◽  
H. J. Lu ◽  
...  
Keyword(s):  
Flip Chip ◽  
Rf Mems ◽  
Bonding Temperature ◽  
Etching Process ◽  
Glass Wafer ◽  
Wafer Level ◽  
Pressure Balance ◽  
Etching Depth ◽  
Wafer Level Packaging ◽  
Via Holes

In this paper, the development of wafer level packaging of radio frequency (RF) microelectromechanical system (MEMS) is reported. The packaging process consists of wafer bonding, wafer thinning, via etching, plating, under-bump-metallization (UBM) and bumping processes. 6-inch Si and glass wafers are used in the study. RF MEMS devices are fabricated on Si wafers and sandwiched between Si and glass cap wafers. To maintain the pressure balance between the cavities and outside world after bonding process, Si and glass wafers are anodically bonded at a pressure of 2 bar and a bonding temperature of 400 °C. The cavities are hermetically sealed. The glass wafer of the bonded pair is thinned down to 100 μm using mechanical polishing and chemical etching, the good uniformity of the wafer thickness is maintained with etching process. A layer of Cr/Au is sputtered and patterned as the hard mask for glass via etching process. Via holes with undercut closer to the etching depth are formed in HF+HNO3 acid. After stripping the metal mask, a seed layer of TiW/Cu is deposited using sputtering and plating processes. TiW layer is used to enhance the adhesion of metal and glass. With the completion of the re-routing and via metallization processes, benzocyclobutene (BCB) photoresist is used to planarize via holes and opened for UBM process. Finally, the packaged devices can be assembled using flip chip approach.

A Packaging Solution for Pressure Sensor MEMS

2003 ◽  
Author(s):  
J. Wei ◽  
G. J. Qi ◽  
Z. F. Wang ◽  
Y. F. Jin ◽  
P. C. Lim ◽  
...  
Keyword(s):  
Pressure Sensor ◽  
Bonding Temperature ◽  
Aluminum Film ◽  
Wafer Level ◽  
Whole Process ◽  
Wafer Level Packaging ◽  
Solder Bumps ◽  
Via Holes ◽  
Free Interfaces ◽  
Koh Etching

In this paper, a wafer-level packaging solution for pressure sensor microelectromechanical system (MEMS) is reported. Sensor and glass cap wafers are anodically bonded at a bonding temperature less than 400°C. Bubble free interfaces are obtained and the bond strength is higher than 20 MPa. Sensor and bottom silicon cap wafers are bonded at a temperature of 400–450°C with the assistance of a gold intermediate layer. The bond strenght is higher than 5 MPa. The via holes, used for feedthroughs leading out the circuit, on bottom silicon cap wafer are anisotropically formed in KOH etching solution. Aluminum layer is sputtered on the bottom silicon wafer for electrical connection, re-routing circuit and the seed layer of under bump metallization (UBM). During sputtering process, the sidewalls of via holes are also sputtered with aluminum film. At the same time, the metal pads on sensor wafer are also built up to connect with metallized via holes. It is found that the cavities are vacuum sealed. Sputtered Cr/Ni/Au layers are used for UBM layers. Finally, solder bumps can printed or plated on the UBM. The whole process leads to promising performance of the devices.

Parametric Design and Reliability Analysis of WIT Wafer Level Packaging

2000 ◽  
Author(s):  
Y. T. Lin ◽  
P. J. Tang ◽  
K. N. Chiang
Keyword(s):  
Reliability Analysis ◽  
Flip Chip ◽  
Parametric Design ◽  
Material Selection ◽  
New Technology ◽  
Rapid Expansion ◽  
Wafer Level ◽  
Good Reliability ◽  
Wafer Level Packaging ◽  
Wafer Level Package

Abstract The demands of electronic packages toward lower profile, lighter weight, and higher density of I/O lead to rapid expansion in the field of flip chip, chip scale package (CSP) and wafer level packaging (WLP) technologies. The urgent needs of high I/O density and good reliability characteristic lead to the evolution of the ultra high-density type of non-solder interconnection such as the wire interconnect technology (WIT). The new technology using copper posts to replace the solder bumps as interconnections shown a great improvement in the reliability life. Moreover, this type of wafer level package could achieve higher I/O density, as well as ultra fine pitch. This research will focus on the reliability analysis of the WIT package structures in material selection and structural design, etc. This research will use finite element method to analyze the physical behavior of packaging structures under thermal cycling condition to compare the reliability characteristics of conventional wafer level package and WIT packages. Parametric studies of specific parameters will be performed, and the plastic and temperature dependent material properties will be applied to all of the models.

Characterization of a Semiconductor Packaging System utilizing Through Glass Via (TGV) Technology

2015 ◽  
Vol 2015 (DPC) ◽  
pp. 001378-001407
Author(s):  
Tim Mobley ◽  
Roupen Keusseyan ◽  
Tim LeClair ◽  
Konstantin Yamnitskiy ◽  
Regi Nocon
Keyword(s):  
Low Cost ◽  
Glass Wafer ◽  
Wafer Level ◽  
Packaging System ◽  
Thin Glass ◽  
Wafer Level Packaging ◽  
Recent Developments ◽  
And Performance ◽  
New Generation ◽  
Semiconductor Packaging

Recent developments in hole formations in glass, metalizations in the holes, and glass to glass sealing are enabling a new generation of designs to achieve higher performance while leveraging a wafer level packaging approach for low cost packaging solutions. The need for optical transparency, smoother surfaces, hermetic vias, and a reliable platform for multiple semiconductors is growing in the areas of MEMS, Biometric Sensors, Medical, Life Sciences, and Micro Display packaging. This paper will discuss the types of glass suitable for packaging needs, hole creation methods and key specifications required for through glass vias (TGV's). Creating redistribution layers (RDL) or circuit layers on both sides of large thin glass wafer poses several challenges, which this paper will discuss, as well as, performance and reliability of the circuit layers on TGV wafers or substrates. Additionally, there are glass-to-glass welding techniques that can be utilized in conjunction with TGV wafers with RDL, which provide ambient glass-to-glass attachments of lids and standoffs, which do not outgas during thermal cycle and allow the semiconductor devices to be attached first without having to reflow at lower temperatures. Fabrication challenges, reliability testing results, and performance of this semiconductor packaging system will be discussed in this paper.

Low Temperature Wafer Level Bonding Using Benzocyclobutene Adhesive Polymers

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 1-24
Author(s):  
Michael Gallagher ◽  
Jong-Uk Kim ◽  
Eric Huenger ◽  
Kai Zoschke ◽  
Christina Lopper ◽  
...  
Keyword(s):  
Low Temperature ◽  
Wafer Bonding ◽  
Flip Chip ◽  
Bonding Temperature ◽  
Bonding Process ◽  
Curing Temperature ◽  
Wafer Level ◽  
Mechanical Adhesion ◽  
3D Stacking ◽  
Dry Etch

3D stacking, one of the 3D integration technologies using through silicon vias (TSVs), is considered as a desirable 3D solution due to its cost effectiveness and matured technical background. For successful 3D stacking, precisely controlled bonding of the two substrates is necessary, so that various methods and materials have been developed over the last decade. Wafer bonding using polymeric adhesives has advantages. Surface roughness, which is critical in direct bonding and metal-to-metal bonding, is not a significant issue, as the organic adhesive can smooth out the unevenness during bonding process. Moreover, bonding of good quality can be obtained using relatively low bonding pressure and low bonding temperature. Benzocyclobutene (BCB) polymers have been commonly used as bonding adhesives due to their relatively low curing temperature (~250 °C), very low water uptake (<0.2%), excellent planarizing capability, and good affinity to Cu metal lines. In this study, we present wafer bonding with BCB at various conditions. In particular, bonding experiments are performed at low temperature range (180 °C ~ 210 °C), which results in partially cured state. In order to examine the effectiveness of the low temperature process, the mechanical (adhesion) strength and dimensional changes are measured after bonding, and compared with the values of the fully cured state. Two different BCB polymers, dry-etch type and photo type, are examined. Dry etch BCB is proper for full-area bonding, as it has low degree of cure and therefore less viscosity. Photo-BCB has advantages when a pattern (frame or via open) is to be structured on the film, since it is photoimageable (negative tone), and its moderate viscosity enables the film to sustain the patterns during the wafer bonding process. The effect of edge beads at the wafer rim area and the soft cure (before bonding) conditions on the bonding quality are also studied. Alan/Rey ok move from Flip Chip and Wafer Level Packaging 1-6-12.

Cost Comparison of Fan-out Wafer Level Packaging and Flip Chip Packaging

2017 ◽  
Vol 2017 (DPC) ◽  
pp. 1-37 ◽  
Author(s):  
Amy Lujan
Keyword(s):  
Flip Chip ◽  
Cost Effective ◽  
Cost Comparison ◽  
Cost Modeling ◽  
Wafer Level ◽  
Design Features ◽  
Wafer Level Packaging ◽  
Flip Chip Packaging ◽  
The Right ◽  
The Cost

In recent years, there has been increased focus on fan-out wafer level packaging with the growing inclusion of a variety of fan-out wafer level packages in mobile products. While fan-out wafer level packaging may be the right solution for many designs, it is not always the lowest cost solution. The right packaging choice is the packaging technology that meets design requirements at the lowest cost. Flip chip packaging, a more mature technology, continues to be an alternative to fan-out wafer level packaging. It is important for many in the electronic packaging industry to be able to determine whether flip chip or fan-out wafer level packaging is the most cost-effective option. This paper will compare the cost of flip chip and fan-out wafer level packaging across a variety of designs. Additionally, the process flows for each technology will be introduced and the cost drivers highlighted. A variety of package sizes, die sizes, and design features will be covered by the cost comparison. Yield is a key component of cost and will also be considered in the analysis. Activity based cost modeling will be used for this analysis. With this type of cost modeling, a process flow is divided into a series of activities, and the total cost of each activity is accumulated. The cost of each activity is determined by analyzing the following attributes: time required, labor required, material required (consumable and permanent), capital required, and yield loss. The goal of this cost comparison is to determine which design features drive a design to be packaged more cost-effectively as a flip chip package, and which design features result in a lower cost fan-out wafer level package.

On the Origins, Status, and Future of Flip Chip & Wafer Level Packaging

2010 ◽  
Vol 2010 (1) ◽  
pp. 000325-000332 ◽  
Author(s):  
Alan Huffman ◽  
Philip Garrou
Keyword(s):  
Technological Change ◽  
Flip Chip ◽  
Emerging Technologies ◽  
Unit Area ◽  
Form Factors ◽  
Electrical Performance ◽  
Wafer Level ◽  
3D Integration ◽  
Wafer Level Packaging ◽  
Area Array

As IC scaling continues to shrink transistors, the increased number of circuits per chip requires more I/O per unit area (Rent's rule). High I/O count, the need for smaller form factors and the need for better electrical performance drove the technological change towards die being interconnected (assembled) by area array techniques. This review will examine this evolution from die wire bonded on lead frames to flip chip die in wafer level or area array packages and discuss emerging technologies such as copper pillar bumps, fan out packaging, integrated passives, and 3D integration..

Fan-Out Wafer-Level Packaging (FOWLP) of Large Chip with Multiple Redistribution Layers (RDLs)

2017 ◽  
Vol 14 (4) ◽  
pp. 123-131 ◽  
Author(s):  
John Lau ◽  
Ming Li ◽  
Nelson Fan ◽  
Eric Kuah ◽  
Zhang Li ◽  
...  
Keyword(s):  
Thin Layer ◽  
Glass Wafer ◽  
Front Side ◽  
Wafer Level ◽  
Molding Compound ◽  
The Third ◽  
Wafer Level Packaging ◽  
Die Attach ◽  
Solder Balls ◽  
Test Package

This study is for fan-out wafer-level packaging with chip-first (die face-up) formation. Chips with Cu contact-pads on the front side and a die attach film on the backside are picked and placed face-up on a temporary-glass-wafer carrier with a thin layer of light-to-heat conversion material. It is followed by compression molding with an epoxy molding compound (EMC) and a post-mold cure on the reconstituted wafer carrier and then backgrinding the molded EMC to expose the Cu contact-pads of the chips. The next step is to build up the redistribution layers (RDLs) from the Cu contact-pads and then mount the solder balls. This is followed by the debonding of the carrier with a laser and then the dicing of the whole reconstituted wafer into individual packages. A 300-mm reconstituted wafer with a package/die ratio = 1.8 and a die-top EMC cap = 100 μm has also been fabricated (a total of 325 test packages on the reconstituted wafer). This test package has three RDLs; the line width/spacing of the first RDL is 5 μm/5 μm, of the second RDL is 10 μm/10 μm, and of the third RDL is 15 μm/15 μm. The dielectric layer of the RDLs is fabricated with a photosensitive polyimide and the conductor layer of the RDLs is fabricated by electrochemical Cu deposition (ECD).

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