Compact Thermal Representations for Several Fundamental Shapes in Forced Convection

Author(s):  
Kyle A. Brucker ◽  
Kyle T. Ressler ◽  
Joseph Majdalani

In the cooling of electronic packages, the task of simulating large arrays of heat sinks is often accomplished by the use of compact models. These simpler models attempt to capture the thermal and flow resistance characteristics of a representative heat sink while ignoring secondary detail. In the porous block model, an equivalent thermal conductivity is assigned to the fluid that enters the ‘porous’ space above the heat sink base that was once occupied by the fins. This artificially enhanced thermal conductivity enables the porous block of fluid to exhibit the same thermal resistance as that of the original heat sink. Due to the three-dimensional distribution of the thermal resistance in space, temperature maps associated with the resulting model provide better agreement with detailed numerical simulations than is possible with other models based on two-dimensional flat plate or thin sheet approximations. In this paper, we present closed-form expressions for the equivalent thermal conductivity associated with a large number of heat sink shapes in a forced convection environment.

Author(s):  
Kyle A. Brucker ◽  
Kyle T. Ressler ◽  
Joseph Majdalani

In this article, general canonical forms for the effective thermal conductivities of compact heat sink models are derived using perturbation tools. The resulting approximations apply to a large number of fundamental heat sink shapes used in natural convection applications. The effective thermal conductivity is a property that can be assigned to the porous block (i.e., volume of fluid) above the heat sink base that was once occupied by the fins. The increased thermal conductivity of the fluid entering the porous block produces a reduced thermal resistance that matches that of the original heat sink. The use of a compact representation is accompanied by substantial computational savings that promote faster optimization and communication between simulation analysts and design engineers. The generalized approximations for the effective thermal conductivity presented here are numerically verified.


2015 ◽  
Vol 2015 (CICMT) ◽  
pp. 000062-000066 ◽  
Author(s):  
T. Welker ◽  
S. Günschmann ◽  
N. Gutzeit ◽  
J. Müller

The integration density in semiconductor devices is significantly increased in the last years. This trend is already described by Moore's law what forecasts a doubling of the integration density every two years. This evolution makes greater demands on the substrate technology which is used for the first level interconnect between the semiconductor and the device package. Higher pattern resolution is required to connect more functions on a smaller chip. Also the thermal performance of the substrate is a crucial issue. The increased integration density leads to an increased power density, what means that more heat has to dissipate on a smaller area. Thus, substrates with a high thermal conductivity (e. g. direct bonded copper (DBC)) are utilized which spread the heat over a large area. However, the reduced pattern resolution caused by thick metal layers is disadvantageous for this substrate technology. Alternatively, low temperature co-fired ceramic (LTCC) can be used. This multilayer technology provides a high pattern resolution in combination with a high integration grade. The poor thermal conductivity of LTCC (3 … 5 W*m−1*K−1) requires thermal vias made of silver paste which are placed between the power chip and the heat sink and reduce the thermal resistance of the substrate. The via-pitch and diameter is limited by the LTCC technology, what allows a maximum filling grade of approx. 20 to 25 %. Alternatively, an opening in the ceramic is created, to bond the chip directly to the heat sink. This leads to technological challenges like the CTE mismatch between the chip and the heat sink material. Expensive materials like copper molybdenum composites with matched CTE have to be used. In the presented investigation, a thick silver tape is used to form a thick silver heat spreader through the LTCC substrate. An opening is structured by laser cutting in the LTCC tape and filled with a laser cut silver tape. After lamination, the substrate is fired using a constraint sintering process. The bond strength of the silver to LTCC interface is approx. 5.6 MPa. The thermal resistance of the silver structure is measured by a thermal test chip (Delphi PST1, 2.5 mm × 2.5 mm) glued with a high thermal conducting epoxy to the silver structure. The chip contains a resistor and diodes to generate heat and to determine the junction temperature respectively. The backside of the test structure is temperature stabilized by a temperature controlled heat sink. The resulting thermal resistance is in the range of 1.1 K/W to 1.5 K/W depending on the length of silver structure (5 mm to 7 mm). Advantages of the presented heat spreader are the low thermal resistance and the good embedding capability in the co-fire LTCC process.


2006 ◽  
Vol 968 ◽  
Author(s):  
Yimin Zhang ◽  
Allison Xiao ◽  
Jeff McVey

ABSTRACTThermal interface materials (TIMs) are used to dissipate thermal energy from a heat-generating device to a heat sink via conduction. The growing power density of the electronic device demands next-generation high thermal conductivity and/or low thermal resistance TIMs. This paper discusses the current state-of-art TIM solutions, particularly fusible particles for improved thermal conductivity. The paper will address the benefits and limitations of this approach, and describe a system with unique filler morphology. Thermal resistance and diffusivity/conductivity characterization techniques are also discussed.


Author(s):  
Afzal Husain ◽  
Mohd Ariz ◽  
Nasser A. Al-Azri ◽  
Nabeel Z. H. Al-Rawahi ◽  
Mohd. Z. Ansari

The increase in the CPV temperature significantly reduces the efficiency of CPV system. To maintain the CPV temperature under a permissible limit and to utilize the unused heat from the CPVs, an efficient cooling and transportation of coolant is necessary in the system. The present study proposes a new design of hybrid jet impingements/microchannels heat sink with pillars for cooling densely packed PV cells under high concentration. A three-dimensional numerical model was constructed to investigate the thermal performance under steady state, incompressible and laminar flow. A constant heat flux was applied at the base of the substrate to imitate heated CPV surface. The effect of two dimensionless variables, i.e., ratios of standoff (distance from the nozzle exit to impingement surface) to jet diameter and jet pitch to jet diameter was investigated at several flow conditions. The performance of hybrid heat sink was investigated in terms of heat transfer coefficient, pressure-drop, overall thermal resistance and pumping power. The characteristic relationship between the overall thermal resistance and the pumping power was presented which showed an optimum design corresponding to S/Dj = 12 having lower overall thermal resistance and lower pumping power.


2015 ◽  
Vol 1092-1093 ◽  
pp. 550-554
Author(s):  
Jian Long Liu ◽  
Jie Nan Xie ◽  
Peng Liu ◽  
Mu Ye Huang

Through the three-dimensional heat transfers numerical simulation of eight kinds with the different number of holes, void ratio and arrangement of sintered shale porous brick (size: 240mm×190mm×90mm), which simulate the sintered porous brick under two different laying way that is 240mm wall and 190mm wall of equivalent thermal conductivity. The result shows: the same kind of porous brick as 240mm wall and 190mm wall, when the equivalent thermal conductivity coefficient has phased difference that the wall insulation effect is obviously different. Through the analysis of two different methods of the masonry wall thermal insulation performance of the influence by different reasons, targeted to put forward some suggestions in order to improve calorific performance of the wall.


Author(s):  
Anjali Chauhan ◽  
Bahgat Sammakia ◽  
Kanad Ghose ◽  
Gamal Refai-Ahmed ◽  
Dereje Agonafer

The stacking of processing and memory components in a three-dimensional (3D) configuration enables the implementation of processing systems with small form factors. Such stacking shortens the interconnection length between processing and memory components to dramatically lower the memory access latencies, and contributes to significant improvements in the memory access bandwidth. Both of these factors elevate overall system performance to levels that are not realizable with prevailing and other proposed solutions. The shorter interconnection lengths in stacked architectures also enable the use of smaller drivers for the interconnections, which in turn reduces interconnection-level energy dissipations. On the down side, stacking of processing and memory components introduces a significant thermal management challenge that is rooted in the high thermal resistance of stacked designs. This paper examines and evaluates three distinct solutions that address thermal management challenges in a system that stacks DRAM components onto a processing core. We primarily focus on three different configurations of a microchannel-based single-phase liquid cooling system with a traditional air-cooled heat sink. Our evaluations, which are intended to study the limits of each solution, assume a uniform power dissipation model for the processor and accounts for the thermal resistance offered by the thermal interface material (TIM), the interconnect layer, and through-silicon vias (TSVs). The liquid-cooled microchannel heat sink shows more promising results when integrated into the package than when added to the microprocessor package from outside.


Author(s):  
Sridhar Narasimhan ◽  
Avram Bar-Cohen

The present work considers the compact modeling of unshrouded parallel plate heat sinks in laminar forced convection. The computational domain includes three heat sinks in series, cooled by an intake fan. The two upstream heat sinks are represented as “porous blocks”, each with an effective thermal conductivity and a pressure loss coefficient, while the downstream heat sink, assumed to be the component requiring the most accurate characterization, is modeled in detail. A large parametric space covering three typical heat sink geometries, as well as a range of common inlet velocities, separation distances between the heat sinks, and bypass clearances is considered in the development and evaluation of the compact models. The current study uses a boundary layer-based methodology, accounting for both the viscous dissipation and form drag losses, to determine the pressure drop characteristics, and an effective conductivity methodology, using a flow bypass model and Nusselt number correlation, to determine the effective thermal conductivity, for the porous block representation of the heat sink. The results indicate that the introduction of compact heat sinks has little influence on the pressure drop of the critical heat sink. Good agreement in pressure drops, typically in the range of 5%, is also obtained between “detailed” heat sink models and their corresponding porous block representation. The introduction of the compact models is found to have little influence (typically less than 1°C) on the base temperature of the critical heat sinks. For the compact heat sinks, the agreement is again within a typical difference of 5% in thermal resistance. Dramatic improvements were observed in the mesh count (factor > 10X) and solution time (factor >20X) required to achieve a high-fidelity simulation of the velocity, pressure, and temperature fields.


2004 ◽  
Vol 126 (4) ◽  
pp. 449-456 ◽  
Author(s):  
K. Ramakrishna ◽  
T.-Y. Tom Lee

Enhancements to thermal performance of FC-PBGA packages due to underfill thermal conductivity, controlled collapse chip connection (C4) pitch, package to printed wiring board (PWB) interconnection through thermal balls, a heat spreader on the backside of the die, and an overmolded die with and without a heat spreader have been studied by solving a conjugate heat transfer problem. These enhancements have been investigated under natural and forced convection conditions for freestream velocities up to 2 m/s. The following ranges of parameters have been covered in this study: substrate size: 25–35 mm, die size: 6.19×7.81 mm (48 mm2 area) and 9.13×12.95 mm (118 mm2 area), underfill thermal conductivity: 0.6–3.0 W/(m K), C4 pitch: 250 μm and below, no thermal balls to 9×9 array of thermal balls on 1.27 mm square pitch, and with copper heat spreader on the back of a bare and an overmolded die. Based on our previous work, predictions in this study are expected to be within ±10% of measured data. The conclusions of the study are: (i) Thermal conductivity of the underfill in the range 0.6 to 10 W/(m K) has negligible effect on thermal performance of FC-PBGA packages investigated here. (ii) Thermal resistances decrease 12–15% as C4 pitch decreases below 250 μm. This enhancement is smaller with increase in die area. (iii) Thermal balls connected to the PTHs in the PWB decrease thermal resistance of the package by 10–15% with 9×9 array of thermal balls and PTHs compared to no thermal balls. The effect of die size on this enhancement is more noticeable on junction to board thermal resistance, Ψjb, than the other two package thermal metrics. (iv) Heat spreader on the back of the die decreases junction-to-ambient thermal resistance, Θja, by 6% in natural convection and by 25% in forced convection. (v) An overmolded die with a heat spreader provides better a thermal enhancement than a heat spreader on a bare die for freestream velocities up to about 1 m/s. Beyond 1 m/s, a heat spreader on bare die has better thermal performance.


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