Simultaneous tracking and low-data-rate communications with high-speed array detectors for optical communications network management

1990 ◽  
Author(s):  
David L. Clark ◽  
Michael A. Cosgrove ◽  
Ralph C. Short ◽  
Mike Thielk ◽  
Randy C. Van Vranken ◽  
...  
Keyword(s):  
Network Management ◽  
Optical Communications ◽  
High Speed ◽  
Data Rate ◽  
Communications Network ◽  
Array Detectors

scholarly journals Inverted p-down Design for High-Speed Photodetectors

Photonics ◽  
2021 ◽  
Vol 8 (2) ◽  
pp. 39
Author(s):  
Masahiro Nada ◽  
Fumito Nakajima ◽  
Toshihide Yoshimatsu ◽  
Yasuhiko Nakanishi ◽  
Atsushi Kanda ◽  
...  
Keyword(s):  
Amplitude Modulation ◽  
Optical Communications ◽  
High Speed ◽  
Pulse Amplitude ◽  
Avalanche Photodiode ◽  
Device Fabrication ◽  
Pulse Amplitude Modulation ◽  
Optical Coupling ◽  
Pin Photodiodes

We discuss the structural consideration of high-speed photodetectors used for optical communications, focusing on vertical illumination photodetectors suitable for device fabrication and optical coupling. We fabricate an avalanche photodiode that can handle 100-Gbit/s four-level pulse-amplitude modulation (50 Gbaud) signals, and pin photodiodes for 100-Gbaud operation; both are fabricated with our unique inverted p-side down (p-down) design.

scholarly journals A 1.55-to-32-Gb/s Four-Lane Transmitter with 3-Tap Feed Forward Equalizer and Shared PLL in 28-nm CMOS

Electronics ◽  
2021 ◽  
Vol 10 (16) ◽  
pp. 1873
Author(s):  
Chen Cai ◽  
Xuqiang Zheng ◽  
Yong Chen ◽  
Danyu Wu ◽  
Jian Luan ◽  
...  
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Data Rate ◽  
Quality Data ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Feed Forward ◽  
Fully Integrated ◽  
Output Driver ◽  
28 Nm

This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual voltage-controlled oscillator (VCO) was integrated to provide the low jitter clock. Each lane with a configurable serialization scheme was adapted to adjust the data rate flexibly. To achieve high-speed data transmission, several bandwidth-extended techniques were introduced, and an optimized output driver with a 3-tap feed-forward equalizer (FFE) was proposed to accomplish high-quality data transmission and equalization. The TX prototype was fabricated in a 28-nm CMOS process, and a single-lane TX only occupied an active area of 0.048 mm2. The shared PLL and clock distribution circuits occupied an area of 0.54 mm2. The proposed PLL can support a tuning range that covers 6.2 to 16 GHz. Each lane's data rate ranged from 1.55 to 32 Gb/s, and the energy efficiency is 1.89 pJ/bit/lane at a 32-Gb/s data rate and can tune an equalization up to 10 dB.

Silicon-based nonlinear optical devices for high-speed optical communications

2008 ◽  
Author(s):  
Haisheng Rong ◽  
Simon Ayotte ◽  
Shengbo Xu ◽  
Oded Cohen ◽  
Mario Paniccia
Keyword(s):  
Optical Communications ◽  
High Speed ◽  
Nonlinear Optical ◽  
Optical Devices ◽  
Nonlinear Optical Devices ◽  
Silicon Based

scholarly journals High speed multi-channel data acquisition technique for efficient hardware utilization using quad data rate approach

2018 ◽  
Vol 7 (4) ◽  
pp. 2569
Author(s):  
Priyanka Chauhan ◽  
Dippal Israni ◽  
Karan Jasani ◽  
Ashwin Makwana
Keyword(s):  
Power Consumption ◽  
Data Acquisition ◽  
Resource Utilization ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
State Of The Art ◽  
Data Rate ◽  
Field Programmable ◽  
Sensor Signals ◽  
Acquisition Technique

Data acquisition is the most demanding application for the acquisition and monitoring of various sensor signals. The data received are processed in real-time environment. This paper proposes a novel Data Acquisition (DAQ) technique for better resource utilization with less power consumption. Present work has designed and compared advanced Quad Data Rate (QDR) technique with traditional Dual Data Rate (DDR) technique in terms of resource utilization and power consumption of Field Programmable Gate Array (FPGA) hardware. Xilinx ISE is used to verify results of FPGA resource utilization by QDR with state of the art DDR approach. The paper ratiocinates that QDR technique outperforms traditional DDR technique in terms of FPGA resource utilization.  

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