The rapid increase in total transmission capacity within and between data centers requires the construction of low-cost, high-capacity optical transmitters. Since a tremendous number of transmitters are required, photonic integrated circuits (PICs) using Si photonics technology enabling the integration of various functional devices on a single chip is a promising solution. A limitation of a Si-based PIC is the lack of an efficient light source due to the indirect bandgap of Si; therefore, hybrid integration technology of III-V semiconductor lasers on Si is desirable. The major challenges are that heterogeneous integration of III-V materials on Si induces the formation of dislocation at high process temperature; thus, the epitaxial regrowth process is difficult to apply. This paper reviews the evaluations conducted on our epitaxial growth technique using a directly bonded III-V membrane layer on a Si substrate. This technique enables epitaxial growth without the fundamental difficulties associated with lattice mismatch or anti-phase boundaries. In addition, crystal degradation correlating with the difference in thermal expansion is eliminated by keeping the total III-V layer thickness thinner than ~350 nm. As a result, various III-V photonic-device-fabrication technologies, such as buried regrowth, butt-joint regrowth, and selective area growth, can be applicable on the Si-photonics platform. We demonstrated the growth of indium-gallium-aluminum arsenide (InGaAlAs) multi-quantum wells (MQWs) and fabrication of lasers that exhibit >25 Gbit/s direct modulation with low energy cost. In addition, selective-area growth that enables the full O-band bandgap control of the MQW layer over the 150-nm range was demonstrated. We also fabricated indium-gallium-arsenide phosphide (InGaAsP) based phase modulators integrated with a distributed feedback laser. Therefore, the directly bonded III-V-on-Si substrate platform paves the way to manufacturing hybrid PICs for future data-center networks.
Development of an Epitaxial Growth Technique Using III-V on a Si Platform for Heterogeneous Integration of Membrane Photonic Devices on Si