Reliability of Flash Nonvolatile Memories

This paper reviews the reliability of Flash nonvolatile memories, with particular to dielectric degradation. These memories are manufactured with the same materials and processing steps as are other types of IC's, but unique features of Flash memories create very different reliability challenges. These features stem from the three unique functions of the Flash cell: to program, to erase, and to retain charge for years. Each of these functions has its own characteristic degradation mechanisms. A fascinating aspect of Flash reliability is the insight that can be gained into dielectric degradation mechanisms. In normal use, Flash dielectries experience levels of electric field, hot-carrier bombardment, and charge fluence that other IC processes experience only in capacitor breakdown studies and other accelerated stresses. Catastrophic breakdown does not occur, however, because the stress from charging and discharging the floating-gate capacitor is fundamentally self-limiting. At the same time, dielectric leakage of a few electrons a day can be measurable in a Flash cell. The combination of high stress, self-limiting degradation, and high leakage sensitivity allows prebreakdown dielectric degradation to be studied in great detail. Although Flash memory technology poses unique development challenges, engineering optimization can make these memories highly reliable.

Download Full-text

Carrier Profiling of the 10-nm-order Structure in a 3D Flash Memory Cell Using Scanning Nonlinear Dielectric Microscopy

ISTFA 2019: Conference Proceedings from the 45th International Symposium for Testing and Failure Analysis ◽

10.31399/asm.cp.istfa2019p0490 ◽

2019 ◽

Author(s):

Jun Hirota ◽

Ken Hoshino ◽

Tsukasa Nakai ◽

Kohei Yamasue ◽

Yasuo Cho

Keyword(s):

Spatial Resolution ◽

Flash Memory ◽

Analytical Techniques ◽

Memory Cell ◽

Memory Device ◽

Floating Gate ◽

Order Structure ◽

Carrier Distribution ◽

Nonlinear Dielectric ◽

Flash Memory Cell

Abstract In this paper, the authors report their successful attempt to acquire the scanning nonlinear dielectric microscopy (SNDM) signals around the floating gate and channel structures of the 3D Flash memory device, utilizing the custom-built SNDM tool with a super-sharp diamond tip. The report includes details of the SNDM measurement and process involved in sample preparation. With the super-sharp diamond tips with radius of less than 5 nm to achieve the supreme spatial resolution, the authors successfully obtained the SNDM signals of floating gate in high contrast to the background in the selected areas. They deduced the minimum spatial resolution and seized a clear evidence that the diffusion length differences of the n-type impurity among the channels are less than 21 nm. Thus, they concluded that SNDM is one of the most powerful analytical techniques to evaluate the carrier distribution in the superfine three dimensionally structured memory devices.

Download Full-text

A Novel High-Stress Pre-Metal Dielectric Film to Improve Device Performance for sub-65nm CMOS Manufacturing

MRS Proceedings ◽

10.1557/proc-0913-d02-01 ◽

2006 ◽

Vol 913 ◽

Author(s):

Young Way Teh ◽

John Sudijono ◽

Alok Jain ◽

Shankar Venkataraman ◽

Sunder Thirupapuliyur ◽

...

Keyword(s):

Performance Improvement ◽

Dielectric Film ◽

High Stress ◽

Significant Degree ◽

Strain Effect ◽

Device Performance ◽

Hot Carrier ◽

Tcad Simulation ◽

Improve Device ◽

Deposition Techniques

AbstractThis work focuses on the development and physical characteristics of a novel dielectric film for a pre-metal dielectric (PMD) application which induces a significant degree of tensile stress in the channel of a sub-65nm node CMOS structure. The film can be deposited at low temperatures to meet the requirements of NiSi integration while maintaining void-free gap fill and superior film quality such as moisture content and uniformity. A manufacturable and highly reliable oxide film has been demonstrated through both TCAD simulation and real device data, showing ~6% NMOS Ion-Ioff improvement; no Ion-Ioff improvement or degradation on PMOS. A new concept has been proposed to explain the PMD strain effect on device performance improvement. Improvement in Hot Carrier immunity is observed compared to similar existing technologies using high density plasma (HDP) deposition techniques.

Download Full-text

Multifunctional molybdenum disulfide flash memory using a PEDOT:PSS floating gate

NPG Asia Materials ◽

10.1038/s41427-021-00307-x ◽

2021 ◽

Vol 13 (1) ◽

Author(s):

Seongin Hong ◽

Junwoo Park ◽

Jung Joon Lee ◽

Sunjong Lee ◽

Kyungho Yun ◽

...

Keyword(s):

Molybdenum Disulfide ◽

Flash Memory ◽

Floating Gate ◽

Bending Test ◽

Light Illumination ◽

Transition Metal Dichalcogenide ◽

Large Memory ◽

Temperature Solution ◽

Multilevel Memory ◽

Floating Layer

AbstractTwo-dimensional transition metal dichalcogenide materials (TMDs), such as molybdenum disulfide (MoS2), have been considered promising candidates for future electronic applications owing to their electrical, mechanical, and optical properties. Here, we present a new concept for multifunctional MoS2 flash memory by combining a MoS2 channel with a PEDOT:PSS floating layer. The proposed MoS2 memory devices exhibit a switching ratio as high as 2.3 × 107, a large memory window (54.6 ± 7.80 V), and high endurance (>1,000 cycles). As the PEDOT:PSS film enables a low-temperature solution-coating process and mechanical flexibility, the proposed P-memory can be embedded on a polyimide substrate over a rigid silicon substrate, offering high mechanical endurance (over 1,000 cycle bending test). Furthermore, both MoS2 and PEDOT:PSS have a bandgap that is desirable in optoelectronic memory operation, where charge carriers are stored differently in the floating gate depending on light illumination. As a new application that combines photodiodes and memory functions, we demonstrate multilevel memory programming based on light intensity and color.

Download Full-text