A COMPUTATIONAL-RAM (C-RAM) ARCHITECTURE FOR REAL-TIME MESH-BASED VIDEO MOTION TRACKING PART 1: MOTION ESTIMATION

2004 ◽  
Vol 13 (06) ◽  
pp. 1203-1215
Author(s):  
MOHAMMED SAYED ◽  
WAEL BADAWY
Keyword(s):  
Motion Estimation ◽  
Real Time ◽  
Motion Tracking ◽  
Cmos Technology ◽  
Block Matching ◽  
Video Frame ◽  
Clock Frequency ◽  
Motion Vectors ◽  
Mesh Structure ◽  
Block Matching Algorithm

This paper presents a new Computational-RAM (C-RAM) architecture for real-time mesh-based video motion tracking. The motion tracking consists of two operations: mesh-based motion estimation and compensation. The proposed motion estimation architecture is presented in Part 1 and the proposed motion compensation architecture is presented in Part 2. The motion estimation architecture stores two frames and computes motion vectors for a regular triangular mesh structure as defined by MPEG-4 Part 2.1 The motion estimation architecture uses the block-matching algorithm (BMA) to estimate the vertical and horizontal motion vectors for each mesh node. Parallel and pipelined implementations have been used to overcome the huge computational requirements of the motion estimation process. The two frames are stored in embedded S-RAMs generated with Virage™ Memory Compiler. The proposed motion estimation architecture has been prototyped, simulated and synthesized using the TSMC 0.18 μm CMOS technology. At 100 MHz clock frequency, the proposed architecture processes one CIF video frame (i.e., 352×288 pixels) in 1.48 ms, which means it can process up to 675 frames per second. The core area of the proposed motion estimation architecture is 24.58 mm2 and it consumes 46.26 mW.

A COMPUTATIONAL-RAM (C-RAM) ARCHITECTURE FOR REAL-TIME MESH-BASED VIDEO MOTION TRACKING PART 2: MOTION COMPENSATION

2004 ◽  
Vol 13 (06) ◽  
pp. 1217-1231
Author(s):  
MOHAMMED SAYED ◽  
WAEL BADAWY
Keyword(s):  
Real Time ◽  
Reference Frame ◽  
Motion Compensation ◽  
Motion Tracking ◽  
Cmos Technology ◽  
Video Frame ◽  
Clock Frequency ◽  
Output Data ◽  
Current Frame ◽  
The Core

This paper presents a new Computational-RAM (C-RAM) architecture for real-time mesh-based video motion tracking. In Part 1, the motion estimation part of the proposed architecture is presented. Here in Part 2, a new C-RAM mesh-based motion compensation architecture is presented. The input data to the architecture is the mesh nodes motion vectors and the reference frame and the output data is the compensated (i.e., predicted) frame. The architecture uses the affine transformation for warping the deformed patches in the reference frame into the undeformed patches in the current frame. The architecture computes the affine parameters using a multiplication-free algorithm. The reference and current frames are stored in embedded S-RAMs generated with Virage™ Memory Compiler. The proposed motion compensation architecture has been prototyped, simulated and synthesized using the TSMC 0.18 μm CMOS technology. Using 100 MHz clock frequency, the proposed architecture processes one CIF video frame (i.e., 352×288 pixels) in 0.59 ms, which means it can process up to 1694 frames per second. The core area of the proposed motion compensation architecture is 28.04 mm2 and it consumes 31.15 mW.

A NOVEL DECOMPOSITION APPROACH AND VLSI IMPLEMENTATION OF CHROMA INTERPOLATOR FOR H.264 ENCODERS

2013 ◽  
Vol 22 (10) ◽  
pp. 1340025
Author(s):  
TENG WANG ◽  
LEI ZHAO ◽  
ZI-YI HU ◽  
ZHENG XIE ◽  
XIN-AN WANG
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Hardware Design ◽  
Cmos Technology ◽  
Vlsi Implementation ◽  
Clock Frequency ◽  
Hardware Cost ◽  
Decomposition Approach ◽  
Lower Power ◽  
Decomposition Scheme

In this paper, a novel decomposition approach and VLSI implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders are proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements (AEs) which are comprised of only adders. Four types of AEs are developed and a pipelining hardware design is proposed to conduct the chroma interpolation with great hardware reuse. The proposed design was prototyped within a Xilinx Virtex6 XC6VLX240T FPGA with a clock frequency as high as 245 MHz. The proposed design was also synthesized with SMIC 130 nm CMOS technology with a clock frequency of 200 MHz, which could support a real-time HDTV application with less hardware cost and lower power consumption.

LOW-POWER 2D MOTION ESTIMATION ARCHITECTURE WITH COMPLEMENTARY EMBEDDED MEMORY BANKS

2000 ◽  
Vol 10 (05n06) ◽  
pp. 229-237
Author(s):  
KYUNG-SAENG KIM ◽  
KWYRO LEE
Keyword(s):  
Motion Estimation ◽  
Data Transfer ◽  
Power Saving ◽  
Block Matching ◽  
Embedded Memory ◽  
Data Transfer Rate ◽  
Matching Algorithm ◽  
Block Matching Algorithm ◽  
Data Reading ◽  
Full Search

This letter describes a motion estimation architecture with complementary access types of memory banks, one for column vector access and the other for row vector access. It handles 2D image very efficiently for full-search block matching algorithm and maximizes a useful data transfer rate by reducing the overhead clocks for extra data reading and alignment. The results show that power saving is improved by using complementary access types of memory banks and amounts to 27.3% when the full-search block matching algorithm is applied for the CCIR-601 format compared to an identical design without the proposed enhancements.

Real-time parking slot availability for Bhavnagar, using statistical block matching approach

2020 ◽  
Vol 17 (6) ◽  
pp. 811-821
Author(s):  
Janak D. Trivedi ◽  
Sarada Devi Mandalapu ◽  
Dhara H. Dave
Keyword(s):  
Real Time ◽  
Region Of Interest ◽  
Mean Value ◽  
Block Matching ◽  
Computational Time ◽  
Maintenance Cost ◽  
Content Type ◽  
Block Matching Algorithm ◽  
The Difference ◽  
Parking Place

Purpose The purpose of this paper is to find a real-time parking location for a four-wheeler. Design/methodology/approach Real-time parking availability using specific infrastructure requires a high cost of installation and maintenance cost, which is not affordable to all urban cities. The authors present statistical block matching algorithm (SBMA) for real-time parking management in small-town cities such as Bhavnagar using an in-built surveillance CCTV system, which is not installed for parking application. In particular, data from a camera situated in a mall was used to detect the parking status of some specific parking places using a region of interest (ROI). The method proposed computes the mean value of the pixels inside the ROI using blocks of different sizes (8 × 10 and 20 × 35), and the values were compared among different frames. When the difference between frames is more significant than a threshold, the process generates “no parking space for that place.” Otherwise, the method yields “parking place available.” Then, this information is used to print a bounding box on the parking places with the color green/red to show the availability of the parking place. Findings The real-time feedback loop (car parking positions) helps the presented model and dynamically refines the parking strategy and parking position to the users. A whole-day experiment/validation is shown in this paper, where the evaluation of the method is performed using pattern recognition metrics for classification: precision, recall and F1 score. Originality/value The authors found real-time parking availability for Himalaya Mall situated in Bhavnagar, Gujarat, for 18th June 2018 video using the SBMA method with accountable computational time for finding parking slots. The limitations of the presented method with future implementation are discussed at the end of this paper.

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