A COMPUTATIONAL-RAM (C-RAM) ARCHITECTURE FOR REAL-TIME MESH-BASED VIDEO MOTION TRACKING PART 2: MOTION COMPENSATION

2004 ◽  
Vol 13 (06) ◽  
pp. 1217-1231
Author(s):  
MOHAMMED SAYED ◽  
WAEL BADAWY
Keyword(s):  
Real Time ◽  
Reference Frame ◽  
Motion Compensation ◽  
Motion Tracking ◽  
Cmos Technology ◽  
Video Frame ◽  
Clock Frequency ◽  
Output Data ◽  
Current Frame ◽  
The Core

This paper presents a new Computational-RAM (C-RAM) architecture for real-time mesh-based video motion tracking. In Part 1, the motion estimation part of the proposed architecture is presented. Here in Part 2, a new C-RAM mesh-based motion compensation architecture is presented. The input data to the architecture is the mesh nodes motion vectors and the reference frame and the output data is the compensated (i.e., predicted) frame. The architecture uses the affine transformation for warping the deformed patches in the reference frame into the undeformed patches in the current frame. The architecture computes the affine parameters using a multiplication-free algorithm. The reference and current frames are stored in embedded S-RAMs generated with Virage™ Memory Compiler. The proposed motion compensation architecture has been prototyped, simulated and synthesized using the TSMC 0.18 μm CMOS technology. Using 100 MHz clock frequency, the proposed architecture processes one CIF video frame (i.e., 352×288 pixels) in 0.59 ms, which means it can process up to 1694 frames per second. The core area of the proposed motion compensation architecture is 28.04 mm2 and it consumes 31.15 mW.

A COMPUTATIONAL-RAM (C-RAM) ARCHITECTURE FOR REAL-TIME MESH-BASED VIDEO MOTION TRACKING PART 1: MOTION ESTIMATION

2004 ◽  
Vol 13 (06) ◽  
pp. 1203-1215
Author(s):  
MOHAMMED SAYED ◽  
WAEL BADAWY
Keyword(s):  
Motion Estimation ◽  
Real Time ◽  
Motion Tracking ◽  
Cmos Technology ◽  
Block Matching ◽  
Video Frame ◽  
Clock Frequency ◽  
Motion Vectors ◽  
Mesh Structure ◽  
Block Matching Algorithm

This paper presents a new Computational-RAM (C-RAM) architecture for real-time mesh-based video motion tracking. The motion tracking consists of two operations: mesh-based motion estimation and compensation. The proposed motion estimation architecture is presented in Part 1 and the proposed motion compensation architecture is presented in Part 2. The motion estimation architecture stores two frames and computes motion vectors for a regular triangular mesh structure as defined by MPEG-4 Part 2.1 The motion estimation architecture uses the block-matching algorithm (BMA) to estimate the vertical and horizontal motion vectors for each mesh node. Parallel and pipelined implementations have been used to overcome the huge computational requirements of the motion estimation process. The two frames are stored in embedded S-RAMs generated with Virage™ Memory Compiler. The proposed motion estimation architecture has been prototyped, simulated and synthesized using the TSMC 0.18 μm CMOS technology. At 100 MHz clock frequency, the proposed architecture processes one CIF video frame (i.e., 352×288 pixels) in 1.48 ms, which means it can process up to 675 frames per second. The core area of the proposed motion estimation architecture is 24.58 mm2 and it consumes 46.26 mW.

A NOVEL DECOMPOSITION APPROACH AND VLSI IMPLEMENTATION OF CHROMA INTERPOLATOR FOR H.264 ENCODERS

2013 ◽  
Vol 22 (10) ◽  
pp. 1340025
Author(s):  
TENG WANG ◽  
LEI ZHAO ◽  
ZI-YI HU ◽  
ZHENG XIE ◽  
XIN-AN WANG
Keyword(s):  
Power Consumption ◽  
Real Time ◽  
Hardware Design ◽  
Cmos Technology ◽  
Vlsi Implementation ◽  
Clock Frequency ◽  
Hardware Cost ◽  
Decomposition Approach ◽  
Lower Power ◽  
Decomposition Scheme

In this paper, a novel decomposition approach and VLSI implementation of the chroma interpolator with great hardware reuse and no multipliers for H.264 encoders are proposed. First, the characteristic of the chroma interpolation is analyzed to obtain an optimized decomposition scheme, with which the chroma interpolation can be realized with arithmetic elements (AEs) which are comprised of only adders. Four types of AEs are developed and a pipelining hardware design is proposed to conduct the chroma interpolation with great hardware reuse. The proposed design was prototyped within a Xilinx Virtex6 XC6VLX240T FPGA with a clock frequency as high as 245 MHz. The proposed design was also synthesized with SMIC 130 nm CMOS technology with a clock frequency of 200 MHz, which could support a real-time HDTV application with less hardware cost and lower power consumption.

scholarly journals A code-aided synchronization IP core for iterative channel decoders

2013 ◽  
Vol 11 ◽  
pp. 137-142 ◽  
Author(s):  
I. Ali ◽  
U. Wasenmüller ◽  
N. Wehn
Keyword(s):  
Communication Systems ◽  
Satellite Communication ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Ip Core ◽  
Unknown Parameters ◽  
Symbol Sequence ◽  
Communication Performance ◽  
The Core ◽  
Channel Decoders

Abstract. Synchronization and channel decoding are integral parts of each receiver in wireless communication systems. The task of synchronization is the estimation of the general unknown parameters of phase, frequency and timing offset as well as correction of the received symbol sequence according to the estimated parameters. The synchronized symbol sequence serves as input for the channel decoder. Advanced channel decoders are able to operate at very low signal-to-noise ratios (SNR). For small values of SNR, the parameter estimation suffers from increased noise and impacts the communication performance. To improve the synchronization quality and thus decoder performance, the synchronizers are integrated into the iterative decoding structure. Intermediate results of the channel decoder after each iteration are used to improve the synchronization. This approach is referred to as code-aided (CA) synchronization or turbo synchronization. A number of CA synchronization algorithms have already been published but there is no publication so far on a generic hardware implementation of the CA synchronization. Therefore we present an algorithm which can be implemented efficiently in hardware and demonstrate its communication performance. Furthermore we present a high throughput, flexible, area and power efficient code-aided synchronization IP core for various satellite communication standards. The core is synthesized for 65 nm low power CMOS technology. After placement and routing the core has an area of 0.194 mm2, throughput of 207 Msymbols/s and consumes 41.4 mW at 300 MHz clock frequency. The architecture is designed in such a way that it does not affect throughput of the system.

Malaria elimination in India requires additional surveillance mechanisms

2021 ◽  
Author(s):  
Manju Rahi ◽  
Payal Das ◽  
Amit Sharma
Keyword(s):  
Real Time ◽  
Malaria Elimination ◽  
Surveillance Data ◽  
Surveillance Systems ◽  
Malaria Surveillance ◽  
Aggregated Data ◽  
Malaria Burden ◽  
The Core ◽  
Reporting Systems ◽  
Geographic Regions

Abstract Malaria surveillance is weak in high malaria burden countries. Surveillance is considered as one of the core interventions for malaria elimination. Impressive reductions in malaria-associated morbidity and mortality have been achieved across the globe, but sustained efforts need to be bolstered up to achieve malaria elimination in endemic countries like India. Poor surveillance data become a hindrance in assessing the progress achieved towards malaria elimination and in channelizing focused interventions to the hotspots. A major obstacle in strengthening India’s reporting systems is that the surveillance data are captured in a fragmented manner by multiple players, in silos, and is distributed across geographic regions. In addition, the data are not reported in near real-time. Furthermore, multiplicity of malaria data resources limits interoperability between them. Here, we deliberate on the acute need of updating India’s surveillance systems from the use of aggregated data to near real-time case-based surveillance. This will help in identifying the drivers of malaria transmission in any locale and therefore will facilitate formulation of appropriate interventional responses rapidly.

scholarly journals The Demonstration of S2P (Serial-to-Parallel) Converter with Address Allocation Method Using 28 nm CMOS Technology

2021 ◽  
Vol 11 (1) ◽  
pp. 429
Author(s):  
Min-Su Kim ◽  
Youngoo Yang ◽  
Hyungmo Koo ◽  
Hansik Oh
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Low Power ◽  
High Speed ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Clock Generation ◽  
Allocation Method ◽  
Evaluation Board ◽  
28 Nm

To improve the performance of analog, RF, and digital integrated circuits, the cutting-edge advanced CMOS technology has been widely utilized. We successfully designed and implemented a high-speed and low-power serial-to-parallel (S2P) converter for 5G applications based on the 28 nm CMOS technology. It can update data easily and quickly using the proposed address allocation method. To verify the performances, an embedded system (NI-FPGA) for fast clock generation on the evaluation board level was also used. The proposed S2P converter circuit shows extremely low power consumption of 28.1 uW at 0.91 V with a core die area of 60 × 60 μm2 and operates successfully over a wide clock frequency range from 5 M to 40 MHz.

Sign in / Sign up

Export Citation Format

Share Document