670-nA CMOS OTA FOR AMLCD COLUMN DRIVER

2009 ◽  
Vol 18 (02) ◽  
pp. 339-350 ◽  
Author(s):  
SALVATORE PENNISI ◽  
SALVATORE DI FAZIO ◽  
TIZIANA SIGNORELLI ◽  
FRANCESCO PULVIRENTI
Keyword(s):  
Operational Amplifier ◽  
Phase Margin ◽  
Slew Rate ◽  
Mos Transistors ◽  
Gain Bandwidth ◽  
Subthreshold Region ◽  
Class Ab ◽  
Dc Gain ◽  
Current Value ◽  
Area Occupation

A transconductance operational amplifier specifically optimized for a switched-capacitor LCD column driver is presented. It exploits MOS transistors in subthreshold region and dissipates 670 nA at DC. Despite this extremely low quiescent current value, the amplifier exhibits a DC gain of about 80 dB, and a gain-bandwidth product and phase margin around 2 MHz and 70°, with a load capacitance of 500 fF. Besides, working in class AB, the solution provides a slew rate equal to 27 V/μs. With exception of the DC gain, these performances represent an improvement with respect to comparable solutions, and are obtained while halving the area occupation.

Design of High Gain CMOS Folded Cascode Operational Amplifier

2013 ◽  
Vol 389 ◽  
pp. 573-578
Author(s):  
Ming Xin Song ◽  
Yue Li ◽  
Meng Meng Xu
Keyword(s):  
Power Supply ◽  
Operational Amplifier ◽  
High Gain ◽  
Cmos Process ◽  
Phase Margin ◽  
Gain Bandwidth ◽  
Input Stage ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

A high-gain folded cascode operational amplifier is presented. Structure of folded cascode operational amplifier and manual calculations are discussed in detail. Folded cascode structure for the input stage is adopted. Folded cascode structure can increase the gain and the value of PSRR. Folded cascode structure can also allow self-compensation at the output. The operational amplifier is designed in 0.35μm CMOS process with 5V power supply. The operational amplifier has high-gain and work steadily. The results of SPICE simulations are shown that the operational amplifier achieved dc gain of 110dB with unity-gain bandwidth of 74.3MHz and phase margin of 54.4 degree.

Multistage Amplifier Using Dual-Miller with Nulling-Resistor and Dual-Feedforward Structure

2014 ◽  
Vol 989-994 ◽  
pp. 1169-1172
Author(s):  
Qian Neng Zhou ◽  
Qi Li ◽  
Jin Zhao Lin ◽  
Hong Juan Li ◽  
Chen Li ◽  
...  
Keyword(s):  
High Gain ◽  
Phase Margin ◽  
Slew Rate ◽  
Well Performance ◽  
Gain Bandwidth ◽  
Wide Bandwidth ◽  
Miller Compensation ◽  
Dc Gain ◽  
Simulation Results ◽  
Multistage Amplifier

This paper designs a high-gain wide-bandwidth multistage amplifier by employing the dual-miller compensation with nulling-resistor and dual-feedforward compensation (DMCNR-DFC) in 0.35μm BCD process. The designed DMCNR-DFC multistage amplifier achieves well performance including gain-bandwidth product (GBW) and slew rate (SR). Simulation results show that the DMCNR-DFC multistage amplifier achieves a dc gain of about 121.1dB and GBW of about 6.1MHz with 52o phase margin.

Two-stage class-AB OTA with enhanced DC gain and slew rate

2016 ◽  
Vol 5 (4) ◽  
pp. 438-448 ◽  
Author(s):  
Seyed Mahmoud Anisheh ◽  
Hossein Shamsi
Keyword(s):  
Slew Rate ◽  
Two Stage ◽  
Class Ab ◽  
Dc Gain ◽  
Stage Class

A LOW POWER CURRENT RECYCLING CONSTANT-gm RAIL-TO-RAIL OTA

2014 ◽  
Vol 23 (02) ◽  
pp. 1450022
Author(s):  
XIAO ZHAO ◽  
HUAJUN FANG ◽  
JUN XU
Keyword(s):  
Low Power ◽  
Bias Current ◽  
Cmos Process ◽  
Slew Rate ◽  
Gain Bandwidth ◽  
Design Specifications ◽  
Rail To Rail ◽  
Dc Gain ◽  
Unity Gain ◽  
Simulation Results

A low power current recycling constant-gm rail-to-rail (RtR) OTA is presented. The proposed amplifier has the benefit of delivering the same performance while consuming half the power compared to the conventional RtR amplifier. This is achieved by recycling the bias current of idle devices, which results in an enhanced transconductance, gain and slew rate. The proposed amplifier was implemented in CSMC standard 0.18 um CMOS process. Simulation results show that the proposed amplifier achieves 10.2 MHz unity-gain bandwidth, 59.4 dB DC gain, 4.8 V/us slew rate and less than 8% deviation in transconductance, but the power consumption reduced by 50% compared to the conventional RtR amplifier with the same design specifications.

A Novel Slew-Boosting Circuit for Rail-to-Rail Operational Amplifier

2020 ◽  
pp. 2150033
Author(s):  
Mingyuan Ren ◽  
Mengying Qin ◽  
Bo Wang ◽  
Xiaowei Han ◽  
Changchun Dong
Keyword(s):  
Operational Amplifier ◽  
Operational Amplifiers ◽  
Tunnel Diodes ◽  
Slew Rate ◽  
Mos Transistors ◽  
Process Measurement ◽  
Level Change ◽  
Rail To Rail ◽  
Measurement Results

In order to improve the slew rate of rail-to-rail operational amplifiers, this paper presents a novel slew boosting circuit. Two slew-boosting unit circuits are proposed to provide large compensation current by directly detecting the differential level change at the input terminals of the amplifier. Accordingly, the slewing performance is dynamically boosted. In each slew-boosting unit circuit, tunnel diodes are used to replace the conventional MOS transistors as loads. This circuit is designed in 1.0[Formula: see text][Formula: see text]m TVS process. Measurement results show that the rail-to-rail operational amplifier achieves a positive slew rate of 164[Formula: see text]V/[Formula: see text]s and negative slew rate of 185[Formula: see text]V/[Formula: see text]s.

Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits

2016 ◽  
Vol 25 (11) ◽  
pp. 1650144 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
Gain Bandwidth ◽  
Class Ab ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Signal Path ◽  
Folded Cascode ◽  
Fast Settling ◽  
Current Shunt

In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.

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