Multi-Path Class AB Operational Amplifier with High Performance for SC Circuits

2016 ◽  
Vol 25 (11) ◽  
pp. 1650144 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
High Performance ◽  
Cmos Technology ◽  
Gain Bandwidth ◽  
Class Ab ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Signal Path ◽  
Folded Cascode ◽  
Fast Settling ◽  
Current Shunt

In this paper, a single-stage multi-path operational transconductance amplifier (OTA) with fast-settling response for high performance applications is designed. The produced amplifier uses current-shunt technique, double recycling structure, cross-coupled positive feedback configuration and all idle devices in the signal path to enhance transconductance of the conventional folded cascode (FC) amplifier. These transconductance boosting techniques lead to higher DC gain, gain bandwidth (GBW), slew rate and lower settling time compared to the previous FC structures while phase margin is degraded. Simulation results are presented using 90 nm CMOS technology which show 1,800% increment in GBW and a 33.2 dB DC gain improvement in the approximately same power consumption compared to the conventional FC amplifier.

High Gain and High CMRR Two-Stage Folded Cascode OTA with Nested Miller Compensation

2015 ◽  
Vol 24 (04) ◽  
pp. 1550057 ◽  
Author(s):  
Meysam Akbari ◽  
Omid Hashemipour
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
High Gain ◽  
Open Loop ◽  
Two Stage ◽  
Miller Compensation ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Folded Cascode

By using Gm-C compensation (GCC) technique, a two-stage recycling folded cascode (FC) operational transconductance amplifier (OTA) is designed. The proposed configuration consists of recycling structure, positive feedback and feed-forward compensation path. In comparison with the typical folded cascode CMOS Miller amplifier, this design has higher DC gain, unity-gain frequency (UGF), slew rate and common mode rejection ratio (CMRR). The presented OTA is simulated in 0.18-μm CMOS technology and the simulation results confirm the theoretical analyses. Finally, the proposed amplifier has a 111 dB open-loop DC gain, 20 MHz UGF and 145 dB CMRR @ 1.2 V supply voltage while the power consumption is 400 μW which makes it suitable for low-voltage applications.

Design of a Gain-Boosted Cascode Amplifier with High Unity-Bandwidth

2014 ◽  
Vol 614 ◽  
pp. 237-240
Author(s):  
Lin Feng Wang ◽  
Qiao Meng ◽  
Hao Zhi
Keyword(s):  
Direct Current ◽  
Cmos Technology ◽  
Gain Bandwidth ◽  
Fully Differential ◽  
Common Mode Voltage ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode ◽  
The Stability ◽  
Cascode Amplifier

This paper presents a high unity gain bandwidth fully differential folded-cascode operational amplifier using gain-boosted technique. The amplifier is designed in TSMC 0.18μm 1P6M CMOS technology. The unity-gain bandwidth (GBW) and poles of the gain-boosting amplifiers were carefully designed to improve the stability. The implemented design provides a direct current (DC) gain of around 93 dB with a unity gain frequency of 1.8GHz. It exhibits a DC gain larger than 88dB when the output common-mode voltage between 0.6 V and 1.2V. the overall layout size is 96μm×120μm.

Design of High Gain Folded Cascode OTA-Based Transconductance–Capacitance Loop Filter for PLL Applications

2021 ◽  
pp. 2150263
Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
High Gain ◽  
Cmos Process ◽  
Operational Transconductance Amplifier ◽  
Loop Filter ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Folded Cascode

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.

Design of a New Low Power Fully Differential Amplifier with Settling Time Enhancement Characteristics

2015 ◽  
Vol 24 (06) ◽  
pp. 1550078 ◽  
Author(s):  
Seid Jafar Hosseinipouya ◽  
Farhad Dastadast
Keyword(s):  
High Performance ◽  
Settling Time ◽  
Cmos Process ◽  
Output Stage ◽  
Common Mode ◽  
Class Ab ◽  
Fully Differential ◽  
Op Amp ◽  
Transconductance Amplifier ◽  
Adaptive Biasing

High performance of fully differential operational transconductance amplifier is designed and implemented using a 0.18-μm CMOS process. The implemented op-amp uses common mode feedback (CMFB) circuit operating in weak inversion region which does not affect other electrical characteristics due to eliminating common mode (CM) levels automatically leading to improve CM rejection ratio (CMRR) of the amplifier significantly. Moreover, the output stage has class-AB operation so that its current can be made larger due to increasing the output current dynamically using adaptive biasing circuit. Additionally, the AC currents of the active loads have been significantly reduced using negative impedances to increase the gain of the amplifier. The results show the GBW 2.3 MHz, slew rate 2.6 V/μs and 1% settling time 150 ns with a capacitive load of 15 pF. This amplifier dissipates only 6.2 μW from a 1.2 V power supply.

scholarly journals Comparative study of symmetrical OTA performance in 180 nm, 130 nm and 90 nm CMOS technology

2019 ◽  
Vol 14 (1) ◽  
pp. 230
Author(s):  
Wan Mohammad Ehsan Aiman Bin Wan Jusoh ◽  
Siti Hawa Ruslan ◽  
Nabihah Ahmad ◽  
Warsuzarina Mat Jubadi ◽  
Rahmat Sanudin
Keyword(s):  
Comparative Study ◽  
Detection System ◽  
Cmos Technology ◽  
Common Mode ◽  
Voltage Supply ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
High Cmrr ◽  
The Comparative Study ◽  
Electrocardiogram Ecg

<span>In this paper, the comparative study of symmetrical Operational Transconductance Amplifier (OTA) performance between 180 nm, 130 nm and 90 nm CMOS technology have been done thoroughly to find the relationship between voltage supply and bias current with performance parameters (gain, power consumption and Common-Mode Rejection Ratio (CMRR)). The OTA which adopts symmetrical topology is designed carefully and simulated using Synopsys HSpice software and the results are carefully analyzed and compared. The symmetrical OTA designed in 90 nm CMOS technology is found to be the best because the power consumed is only 9.83 µW from ±0.9 V voltage supply and the OTA achieved 55.9 dB of the DC gain. The CMRR of the symmetrical 90 nm OTA is 140 dB which is sufficient to reject the common-mode signals in electrocardiogram (ECG) input signal. The symmetrical 90 nm OTA is suitable to be implemented as bioamplifier in ECG signal detection system as it consumed low power and has a high CMRR characteristic.</span>

scholarly journals 0.5 V CMOS Inverter-Based Transconductance Amplifier with Quiescent Current Control

2021 ◽  
Vol 11 (4) ◽  
pp. 37
Author(s):  
Andrea Ballo ◽  
Salvatore Pennisi ◽  
Giuseppe Scotti
Keyword(s):  
Supply Voltage ◽  
Current Control ◽  
Cmos Inverter ◽  
Class Ab ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Unity Gain ◽  
Quiescent Current ◽  
Bulk Technology ◽  
Inverter Topology

A two-stage CMOS transconductance amplifier based on the inverter topology, suitable for very low supply voltages and exhibiting rail-to-rail output capability is presented. The solution consists of the cascade of a noninverting and an inverting stage, both characterized by having only two complementary transistors between the supply rails. The amplifier provides class-AB operation with quiescent current control obtained through an auxiliary loop that utilizes the MOSFETs body terminals. Simulation results, referring to a commercial 28 nm bulk technology, show that the quiescent current of the amplifier can be controlled quite effectively, even adopting a supply voltage as low as 0.5 V. The designed solution consumes around 500 nA of quiescent current in typical conditions and provides a DC gain of around 51 dB, with a unity gain frequency of 1 MHz and phase margin of 70 degrees, for a parallel load of 1 pF and 1.5 MΩ. Settling time at 1% is 6.6 μs, and white noise is 125 nV/Hz.

Low Power Operational Transconductance Amplifier (OTA) with Enhanced DC Gain and Slew-Rate

2013 ◽  
Vol 411-414 ◽  
pp. 1645-1648
Author(s):  
Xiao Zong Huang ◽  
Lun Cai Liu ◽  
Jian Gang Shi ◽  
Wen Gang Huang ◽  
Fan Liu ◽  
...  
Keyword(s):  
Low Voltage ◽  
Cmos Technology ◽  
Optimization Techniques ◽  
Current Mirror ◽  
Slew Rate ◽  
Operational Transconductance Amplifier ◽  
Theory Analysis ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Simulation Results

This paper presents a low-voltage differential operational transconductance amplifier (OTA) with enhanced DC gain and slew-rate. Based on the current mirror OTA topology, the optimization techniques are discussed in this work. The proposed structure achieves enhanced DC gain, unit gain frequency (UGF) and slew-rate (SR) with adding four devices. The design of the OTA is described with theory analysis. The OTA operates at the power supply of 1.8V. Simulation results for 0.18μm standard CMOS technology show that the DC gain increases from 60.6dB to 65dB, the UGF is optimized from 2.5MHz to 4.3MHz, the SR is enhanced from 0.88 V/μs to 4.8 V/μs with close power consumption dramatically.

scholarly journals Single-Stage Operational Transconductance Amplifier Design in UTBSOI Technology Based on gm/Id Methodology

2019 ◽  
Vol 23 (2) ◽  
Author(s):  
Rekib Uddin Ahmed ◽  
Eklare Akshay Vijaykumar ◽  
Prabir Saha
Keyword(s):  
Graphical Models ◽  
Cmos Technology ◽  
Single Stage ◽  
Silicon On Insulator ◽  
Short Channel ◽  
Transconductance Amplifier ◽  
Dc Gain ◽  
Channel Effects ◽  
Performance Specifications ◽  
Amplifier Design

The downscaling of complementary metal-oxidesemiconductor (CMOS) technology is approaching its limits imposed by short-channel effects (SCE), thereby multi-gate MOSFETs have been proposed to extend the scalability. Ultrathin-body silicon-on-insulator (UTBSOI) transistor is one of the dual-gated devices which offers better immunity towards SCEs. In this paper, two designs have been proposed for single-stage operational transconductance amplifiers (OTA) using the CMOS and UTBSOI. The CMOS based OTA (CMOS-OTA) has been designed where sizing (W/L) of the constituting MOSFETs have been evaluated through gm/Id methodology and the same OTA topology has been simulated using UTBSOI (UTBSOI-OTA) considering the same W/L. The DC simulation is carried out over the BSIM3v3 model to store the operating point parameters in the form of graphical models. The mathematical expressions for performance specifications have been applied over the graphical models to evaluate the required W/L. Individual comparisons between the two proposed designs have also been carried out for further applications. Based on simulation results at the schematic level, the UTBSOI-OTA has higher DC gain of 33.26% and lesser power consumption of 2.81% over the CMOS-OTA. Moreover, comparative analysis of performance parameters like DC gain and common-mode rejection ratio (CMRR), have been compared with the best-reported paper so far. In addition to this, the UTBSOI-OTA has been applied to practical integrator circuits for further verification.

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