scholarly journals Ultra-Wide Band LNA Design using Active Inductor with Modified Noise Cancellation Technique

2019 ◽  
Vol 8 (2) ◽  
pp. 2406-2410
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Ultra Wide Band ◽  
Active Inductor ◽  
Cmos Process ◽  
Chip Area ◽  
Chip Size ◽  
Lna Design

An Ultra-Wide Band (UWB) Low Noise Amplifier (LNA) is affective in deciding the chip size and in the implementation cost at Radio Frequency applications. The proposed LNA design with an active inductor is a different solution to trounce the habit of passive inductors to cut the chip area. Designed in 90-nm CMOS process, a voltage gain of 9dB to 15.5dB for a supply voltage of 0.9v to 1.8V with a smallest Noise Figure (NF) of 5.7dB is achieved by the LNA, with low power utilization and at 2.40 GHz, with 345um2 of chip area.

Ground-Adjustable Inductor for Wide-Tuning VCO Design

2012 ◽  
Vol 256-259 ◽  
pp. 2373-2378
Author(s):  
Wu Shiung Feng ◽  
Chin I Yeh ◽  
Ho Hsin Li ◽  
Cheng Ming Tsao
Keyword(s):  
Power Consumption ◽  
Tuning Range ◽  
Supply Voltage ◽  
Wide Band ◽  
Ultra Wide Band ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Wide Tuning Range ◽  
Chip Area ◽  
Ground Plate

A wide-tuning range voltage-controlled oscillator (VCO) with adjustable ground-plate inductor for ultra-wide band (UWB) application is presented in this paper. The VCO was implemented by standard 90nm CMOS process at 1.2V supply voltage and power consumption of 6mW. The tuning range from 13.3 GHz to 15.6 GHz with phase noise between -99.98 and -115dBc/Hz@1MHz is obtained. The output power is around -8.7 to -9.6dBm and chip area of 0.77x0.62mm2.

scholarly journals Design of Low Power UWB CMOS Low Noise Amplifier using Active Inductor for WLAN Receiver

2018 ◽  
Vol 7 (2.24) ◽  
pp. 448
Author(s):  
S Manjula ◽  
M Malleshwari ◽  
M Suganthy
Keyword(s):  
Low Power ◽  
Noise Figure ◽  
Wide Band ◽  
Cmos Technology ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Design System ◽  
Active Inductor ◽  
Chip Area ◽  
Noise Amplifier

This paper presents a low power Low Noise Amplifier (LNA) using 0.18µm CMOS technology for ultra wide band (UWB) applications. gm boosting common gate (CG) LNA is designed to improve the noise performance.  For the reduction of on chip area, active inductor is employed at the input side of the designed LNA for input impedance matching. The proposed UWB LNA is designed using Advanced Design System (ADS) at UWB frequency of 3.1-10.6 GHz. Simulation results show that the gain of 10.74+ 0.01 dB, noise figure is 4.855 dB, input return loss <-13 dB and 12.5 mW power consumption.  

A FULLY INTEGRATED MULTIBAND CMOS 0.35 μM LNA FOR IEEE802.16 STANDARD

2013 ◽  
Vol 22 (02) ◽  
pp. 1250088 ◽  
Author(s):  
MERIAM BEN AMOR ◽  
MOURAD LOULOU ◽  
SEBASTIEN QUINTANEL ◽  
DANIEL PASQUET
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Cmos Process ◽  
Frequency Range ◽  
Fully Integrated ◽  
Input Matching ◽  
Noise Amplifier ◽  
Chebyshev Filter

In this paper we present the design of a fully integrated low noise amplifier for WiMAX standard with AMS 0.35 μm CMOS process. This LNA is designed to cover the frequency range for licensed and unlicensed bands of the WiMAX 2.3–5.9 GHz. The proposed amplifier achieves a wide band input and output matching with S11 and S22 lower than -10 dB, a flat gain of 12 dB and a noise figure around 3.5 dB for the entire band and from the upper to the higher frequencies. The presented wide band LNA employs a Chebyshev filter for input matching and an inductive shunt feedback for output matching with a bias current of 15 mA and a supply voltage of 2.5 V.

scholarly journals Research and Design of X-band Low Noise Amplifier Based on CMOS Process

2021 ◽  
Vol 2108 (1) ◽  
pp. 012102
Author(s):  
Chao Ma ◽  
Hongjiang Wu ◽  
Xudong Lu ◽  
Haitao Sun
Keyword(s):  
Noise Figure ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Center Frequency ◽  
Cmos Process ◽  
Actual Measurement ◽  
Chip Area ◽  
Chip Size ◽  
Noise Amplifier ◽  
Stage Matching

Abstract Based on CMOS process, a low noise amplifier(LNA) operating at 7.4GHz~11.4GHz was designed. The two-stage differential cascode structure is adopted. Transformer was used to achieve inter-stage matching. Balun was used to achieve input and output matching, which reduces the number of inductors used, effectively reduces the chip size while ensuring good gain and noise figure. The actual measurement results show that the power gain at the center frequency of 9.4GHz is 27dB, the maximum noise figure is less than 3.82dB, the output power 1dB compression point is greater than 8dBm, the chip area is only 0.41mm×0.83mm(excluding PAD).

A 1.2 V CMOS COMMON-GATE LOW NOISE AMPLIFIER FOR UWB WIRELESS COMMUNICATIONS

2013 ◽  
Vol 22 (07) ◽  
pp. 1350052 ◽  
Author(s):  
HOSEIN ALAVI-RAD ◽  
SOHEYL ZIABAKHSH ◽  
MUSTAPHA C. E. YAGOUB
Keyword(s):  
Reflection Coefficient ◽  
Noise Figure ◽  
Supply Voltage ◽  
Wide Band ◽  
Low Noise ◽  
Low Noise Amplifier ◽  
Ultra Wide Band ◽  
Band Frequency ◽  
Common Gate ◽  
Noise Amplifier

In this paper, an ultra-wide band 0.18 μm CMOS common-gate low-noise amplifier (LNA) is presented. Designed in the ultra-wide band frequency range of 3.1–10.6 GHz, it uses a current-reused technique with modified input matching. This approach allowed obtaining a flat broadband gain of 12.75 ± 0.83 dB with an input reflection coefficient less than -5.5 dB, an output reflection coefficient less than -7 dB, and a noise figure less than 3.7 dB. Furthermore, the proposed low-power LNA consumes only 12.14 mW (excluding buffer) from a 1.2 V supply voltage.

Design of 3.1-10.6GHz CMOS LNA Based on Input Matching Technique of Common-Gate Topology

2013 ◽  
Vol 479-480 ◽  
pp. 1014-1017
Author(s):  
Yi Cheng Chang ◽  
Meng Ting Hsu ◽  
Yu Chang Hsieh
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
Average Power ◽  
Wide Band ◽  
Low Noise ◽  
Input Matching ◽  
Common Gate ◽  
Cmos Lna ◽  
Noise Amplifier ◽  
Is Design

In this study, three stage ultra-wide-band CMOS low-noise amplifier (LNA) is presented. The UWB LNA is design in 0.18μm TSMC CMOS technique. The LNA input and output return loss are both less than-10dB, and achieved 10dB of average power gain, the minimum noise figure is 6.55dB, IIP3 is about-9.5dBm. It consumes 11mW from a 1.0-V supply voltage.

High Gain and Low Noise Single Balanced Wireless Receiver Front-End Circuit Design

2013 ◽  
Vol 284-287 ◽  
pp. 2647-2651
Author(s):  
Zhe Yang Huang ◽  
Che Cheng Huang ◽  
Jung Mao Lin ◽  
Chung Chih Hung
Keyword(s):  
Return Loss ◽  
Noise Figure ◽  
High Gain ◽  
Low Noise ◽  
Total Power ◽  
Cmos Process ◽  
Chip Area ◽  
Wireless Receiver ◽  
Front End ◽  
Total Power Consumption

This paper presents a wideband wireless receiver front-end for 3.1-5.0GHz band group-1 (BG-1) WiMedia application. The front-end circuits are designed in 0.18um standard CMOS process. The experimental results show the maximum conversion power gain is 45.5dB; minimum noise figure is 2.9dB. Input return loss is lower than -9.3dB and output return loss is lower than -6.8dB. The maximum LO conversion power is 0dBm. 3dB working frequency is 1.9GHz (3.1GHz-5.0GHz) Total power consumption is 24.3mW including LNA, mixer and all buffers. Total chip area is 1.27mm2 including dummy and pads.

scholarly journals A Low-Band Multi-Gain LNA Design for Diversity Receive Module with 1.2 dB NF

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8340
Author(s):  
Behnam S. Rikan ◽  
David Kim ◽  
Kyung-Duk Choi ◽  
Seyed Ali H. Asl ◽  
Joon-Mo Yoo ◽  
...  
Keyword(s):  
Noise Figure ◽  
Supply Voltage ◽  
High Gain ◽  
Low Noise ◽  
Drop Out ◽  
Common Source ◽  
Frequency Bands ◽  
Voltage Compensator ◽  
Current Consumption ◽  
Lna Design

This paper presents and discusses a Low-Band (LB) Low Noise Amplifier (LNA) design for a diversity receive module where the application is for multi-mode cellular handsets. The LB LNA covers the frequency range between 617 MHz to 960 MHz in 5 different frequency bands and a 5 Pole Single Throw (5PST) switch selects the different frequency bands where two of them are for the main and three for the auxiliary bands. The presented structure covers the gain modes from −12 to 18 dB with 6 dB gain steps where each gain mode has a different current consumption. In order to achieve the Noise Figure (NF) specifications in high gain modes, we have adopted a cascode Common-Source (CS) with inductive source degeneration structure for this design. To achieve the S11 parameters and current consumption specifications, the core and cascode transistors for high gain modes (18 dB, 12 dB, and 6 dB) and low gain modes (0 dB, −6 dB, and −12 dB) have been separated. Nevertheless, to keep the area low and keep the phase discontinuity within ±10∘, we have shared the degeneration and load inductors between two cores. To compensate the performance for Process, Voltage, and Temperature (PVT) variations, the structure applies a Low Drop-Out (LDO) regulator and a corner case voltage compensator. The design has been proceeded in a 65-nm RSB process design kit and the supply voltage is 1 V. For 18 dB and −12 dB gain modes as two examples, the NF, current consumption, and Input Third Order Intercept Point (IIP3) values are 1.2 dB and 16 dB, 10.8 mA and 1.2 mA, and −6 dBm and 8 dBm, respectively.

A 1.8 to 4 GHz inductor-less highly linear CMOS LNA for wire-less receivers

2021 ◽  
pp. 11-20
Author(s):  
Nguyen Huu Tho
Keyword(s):  
Noise Figure ◽  
Impedance Matching ◽  
Wide Band ◽  
Low Noise ◽  
Common Source ◽  
Cmos Process ◽  
Wide Range ◽  
Active Feedback ◽  
Cmos Lna ◽  
Noise Amplifier

This paper presents an inductor-less wide-band highly linear low-noise amplifier (LNA) for wire-less receivers. The inductor-less LNA consists of a complementary current-reuse common source amplifier combined with a low-current active feedback to obtain wide range input impedance matching and low noise figure. In our LNA, a degeneration resistor is utilized to improve linearity of the LNA. Furthermore, we designed a bypass mode for the LNA to extend the range of its applications. The proposed LNA is implemented in 28 nm CMOS process. It has a gain of 14.9 dB and a bandwidth of 2.2 GHz. The noise figure (NF) is 1.95 dB and the third-order input intercept point (IIP3) is 24.8 dBm at 2.3 GHz. It consumes 17.2 mW at a 0.9-V supply and has an area of 0.011 mm2.

Sign in / Sign up

Export Citation Format

Share Document