Analysis and Design Procedure of a Novel Low Power Highly Linear Operational Transconductance Amplifier

2015 ◽  
Vol 24 (05) ◽  
pp. 1550071
Author(s):  
Farzan Rezaei ◽  
Seyed Javad Azhari

In this paper, a new highly linear operational transconductance amplifier (OTA) is presented. Proposed OTA employs two linearization techniques of cross-coupled double differential pairs and resistive source degeneration to achieve highly linear response under low power consumption. Considering the linearity and the frequency response issues as main parameters of OTA in the communication circuits, design procedure is theoretically formulated for the best linearity and optimum frequency compensation. Proposed OTA is simulated in 0.18-μm TSMC CMOS technology by Hspice simulator. While, the power consumption is only 467 μW, applying two-tone input voltage with amplitude of 0.6 Vp-p at 10 MHz frequency results in -61 dB third-order intermodulation (IM3) distortion of the output current that still remains below -44 dB for amplitudes up to 1 Vp-p. A precise frequency response analysis is performed which has resulted in optimum values of resistor and capacitor for miller compensation. Using common mode feedback in both stages and push-pull based output stage lead to 108 dB CMRR at DC that decreases to 84.5 dB at 100 kHz frequency.

2014 ◽  
Vol 2014 ◽  
pp. 1-7 ◽  
Author(s):  
Ziad Alsibai ◽  
Salma Bay Abo Dabbous

A new ultra-low-voltage (LV) low-power (LP) bulk-driven quasi-floating-gate (BD-QFG) operational transconductance amplifier (OTA) is presented in this paper. The proposed circuit is designed using 0.18 μm CMOS technology. A supply voltage of ±0.3 V and a quiescent bias current of 5 μA are used. The PSpice simulation result shows that the power consumption of the proposed BD-QFG OTA is 13.4 μW. Thus, the circuit is suitable for low-power applications. In order to confirm that the proposed BD-QFG OTA can be used in analog signal processing, a BD-QFG OTA-based diodeless precision rectifier is designed as an example application. This rectifier employs only two BD-QFG OTAs and consumes only 26.8 μW.


2013 ◽  
Vol 6 (2) ◽  
pp. 109-113 ◽  
Author(s):  
Andrea Malignaggi ◽  
Amin Hamidian ◽  
Georg Boeck

The present paper presents a fully differential 60 GHz four stages low-noise amplifier for wireless applications. The amplifier has been optimized for low-noise, high-gain, and low-power consumption, and implemented in a 90 nm low-power CMOS technology. Matching and common-mode rejection networks have been realized using shielded coplanar transmission lines. The amplifier achieves a peak small-signal gain of 21.3 dB and an average noise figure of 5.4 dB along with power consumption of 30 mW and occupying only 0.38 mm2pads included. The detailed design procedure and the achieved measurement results are presented in this work.


Author(s):  
Priti Gupta ◽  
Sanjay Kumar Jana

This paper deals with the designing of low-power transconductance–capacitance-based loop filter. The folded cascode-based operational transconductance amplifier (OTA) is designed in this paper with the help of quasi-floating bulk MOSFET that achieved the DC gain of 88.61[Formula: see text]dB, unity gain frequency of 97.86[Formula: see text]MHz and power consumption of 430.62[Formula: see text][Formula: see text]W. The proposed OTA is compared with the exiting OTA structure which showed 19.50% increase in DC gain and 15.11% reduction in power consumption. Further, the proposed OTA is used for the designing of transconductance–capacitance-based loop filter that has been operated at [Formula: see text]3[Formula: see text]dB cut-off frequency of 30.12[Formula: see text]MHz with the power consumption of 860.90[Formula: see text][Formula: see text]W at the supply voltage of [Formula: see text][Formula: see text]V. The transistor-level simulation has been done in 0.18[Formula: see text][Formula: see text]m CMOS process.


Author(s):  
G. Biancuzzi ◽  
T. Lemke ◽  
F. Goldschmidtboeing ◽  
O. Ruthmann ◽  
H.-J. Schrag ◽  
...  

The German Artificial Sphincter System (GASS) project aims at the development of an implantable sphincter prosthesis driven by a micropump. During the last few years the feasibility of the concept has been proven. At present our team’s effort is focused on the compliance to safety regulations and on a very low power consumption of the system as a whole. Therefore a low-voltage multilayer piezoactuator has been developed to reduce the driving voltage of the micropump from approximately 300 Vpp to 40 Vpp. Doing so, the driving voltage is within the limits set by the regulations for active implants. The operation of the micropump at lower voltages, achieved using multilayer piezoactuators, has already resulted in a much better power efficiency. Nevertheless, in order to further reduce power consumption, we have also developed an innovative driving technique that we are going to describe and compare to other driving systems. A direct switching circuit has been developed where the buffer capacitor of the step-up converter has been replaced by the equivalent capacitance of the actuator itself. This avoids the switching of the buffer capacitor to the actuator, which would result in a very low efficiency. Usually, a piezoactuator needs a bipolar voltage drive to achieve maximum displacement. In our concept, the voltage inversion across the actuator is done using an h-bridge circuit, allowing the employment of one step-up converter only. The charge stored in the actuator is then partially recovered by means of a step-down converter which stores back the energy at the battery voltage level. The power consumption measurements of our concept are compared to a conventional driving output stage and also with inductive charge recovery circuits. In particular, the main advantage, compared to the latter systems, consists in the small inductors needed for the power converter. Other charge recovery techniques require very big inductors in order to have a significant power reduction with the capacitive loads we use in our application. With our design we will be able to achieve approximately 55% reduction in power consumption compared to the simplest conventional driver and 15% reduction compared to a charge recovery driver.


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