Low Power Electronics for Square-Wave Piezoactuator Driving

2009 ◽  
Author(s):  
G. Biancuzzi ◽  
T. Lemke ◽  
F. Goldschmidtboeing ◽  
O. Ruthmann ◽  
H.-J. Schrag ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Efficiency ◽  
Low Voltage ◽  
Power Converter ◽  
Driving Voltage ◽  
Output Stage ◽  
Maximum Displacement ◽  
Artificial Sphincter ◽  
Charge Recovery

The German Artificial Sphincter System (GASS) project aims at the development of an implantable sphincter prosthesis driven by a micropump. During the last few years the feasibility of the concept has been proven. At present our team’s effort is focused on the compliance to safety regulations and on a very low power consumption of the system as a whole. Therefore a low-voltage multilayer piezoactuator has been developed to reduce the driving voltage of the micropump from approximately 300 Vpp to 40 Vpp. Doing so, the driving voltage is within the limits set by the regulations for active implants. The operation of the micropump at lower voltages, achieved using multilayer piezoactuators, has already resulted in a much better power efficiency. Nevertheless, in order to further reduce power consumption, we have also developed an innovative driving technique that we are going to describe and compare to other driving systems. A direct switching circuit has been developed where the buffer capacitor of the step-up converter has been replaced by the equivalent capacitance of the actuator itself. This avoids the switching of the buffer capacitor to the actuator, which would result in a very low efficiency. Usually, a piezoactuator needs a bipolar voltage drive to achieve maximum displacement. In our concept, the voltage inversion across the actuator is done using an h-bridge circuit, allowing the employment of one step-up converter only. The charge stored in the actuator is then partially recovered by means of a step-down converter which stores back the energy at the battery voltage level. The power consumption measurements of our concept are compared to a conventional driving output stage and also with inductive charge recovery circuits. In particular, the main advantage, compared to the latter systems, consists in the small inductors needed for the power converter. Other charge recovery techniques require very big inductors in order to have a significant power reduction with the capacitive loads we use in our application. With our design we will be able to achieve approximately 55% reduction in power consumption compared to the simplest conventional driver and 15% reduction compared to a charge recovery driver.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Rack Server Solution in Data Center

2015 ◽  
Author(s):  
Sheng Kang ◽  
Guofeng Chen ◽  
Chun Wang ◽  
Ruiquan Ding ◽  
Jiajun Zhang ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Supply ◽  
Data Center ◽  
Power Efficiency ◽  
High Performance ◽  
High Efficiency ◽  
High Growth ◽  
General Purpose ◽  
Power Supplies

With the advent of big data and cloud computing solutions, enterprise demand for servers is increasing. There is especially high growth for Intel based x86 server platforms. Today’s datacenters are in constant pursuit of high performance/high availability computing solutions coupled with low power consumption and low heat generation and the ability to manage all of this through advanced telemetry data gathering. This paper showcases one such solution of an updated rack and server architecture that promises such improvements. The ability to manage server and data center power consumption and cooling more completely is critical in effectively managing datacenter costs and reducing the PUE in the data center. Traditional Intel based 1U and 2U form factor servers have existed in the data center for decades. These general purpose x86 server designs by the major OEM’s are, for all practical purposes, very similar in their power consumption and thermal output. Power supplies and thermal designs for server in the past have not been optimized for high efficiency. In addition, IT managers need to know more information about servers in order to optimize data center cooling and power use, an improved server/rack design needs to be built to take advantage of more efficient power supplies or PDU’s and more efficient means of cooling server compute resources than from traditional internal server fans. This is the constant pursuit of corporations looking at new ways to improving efficiency and gaining a competitive advantage. A new way to optimize power consumption and improve cooling is a complete redesign of the traditional server rack. Extracting internal server power supplies and server fans and centralizing these within the rack aims to achieve this goal. This type of design achieves an entirely new low power target by utilizing centralized, high efficiency PDU’s that power all servers within the rack. Cooling is improved by also utilizing large efficient rack based fans for airflow to all servers. Also, opening up the server design is to allow greater airflow across server components for improved cooling. This centralized power supply breaks through the traditional server power limits. Rack based PDU’s can adjust the power efficiency to a more optimum point. Combine this with the use of online + offline modes within one single power supply. Cold backup makes data center power to achieve optimal power efficiency. In addition, unifying the mechanical structure and thermal definitions within the rack solution for server cooling and PSU information allows IT to collect all server power and thermal information centrally for improved ease in analyzing and processing.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

scholarly journals Power-Efficient Driver Circuit for Piezo Electric Actuator with Passive Charge Recovery

Energies ◽  
2020 ◽  
Vol 13 (11) ◽  
pp. 2866 ◽  
Author(s):  
Takashi Ozaki ◽  
Norikazu Ohta
Keyword(s):  
Power Consumption ◽  
Piezoelectric Actuator ◽  
Power Efficiency ◽  
Parasitic Capacitance ◽  
Passive Components ◽  
Power Efficient ◽  
Electric Actuator ◽  
Driver Circuit ◽  
Aerial Vehicle ◽  
Charge Recovery

Piezoelectric actuation is a promising principle for insect-scaled robots. A major concern while utilizing a piezoelectric actuator is energy loss due to its parasitic capacitance. In this paper, we propose a new concept to recover the charge stored in the parasitic capacitance; it requires only three additional lightweight passive components: two diodes and a resistor. The advantages of our concept are its small additional mass and simple operating procedure compared with existing charge recovery circuits. We provided a guideline for selecting a resistor using a simplified theoretical model and found that half of the charge can be recovered by employing a resistor that has a resistance sufficiently larger than the forward resistance of the additional diode. In addition, we experimentally demonstrated the concept. With a capacitive load (as a replacement for the piezoelectric actuator), it was successfully observed that the proposed concept decreased the power consumption to 58% of that in a circuit without charge recovery. Considering micro aerial vehicle (MAV) applications, we measured the lift-to-power efficiency of a flapping wing piezoelectric actuator by applying the proposed concept. The lift force was not affected by charge recovery; however, the power consumption was reduced. As a result, the efficiency was improved to 30.0%. We expect that the proposed circuit will contribute to the advancement of energy-saving microrobotics.

scholarly journals Novel Low Voltage and Low Power Array Multiplier Design for IoT Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1429 ◽  
Author(s):  
Jin-Fa Lin ◽  
Cheng-Yu Chan ◽  
Shao-Wei Yu
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Full Adder ◽  
Total Power ◽  
Iot Applications ◽  
Delay Cell ◽  
Total Power Consumption ◽  
Array Multiplier ◽  
Cell Circuit

In this paper, a novel latch-adder based multiplier design, targeting low voltage and low power IoT applications is presented. It employs a semi-dynamic (dynamic circuit with static keeper circuit) full adder design which efficiently incorporates the level sensitive latch circuit with the adder cell. Latch circuit control signals are generated by a chain of delay cell circuits. They are applied to each row of the adder array. This row-wise alignment ensures an orderly procedure, while successfully removing spurious switching resulting in reduced power consumption. Due to the delay cell circuit of our design is also realized by using full adder. Therefore, it is unnecessary to adjust the transistor sizes of the delay cell circuit deliberately. Post-layout simulation results on 8 × 8 multiplier design show that the proposed design has the lowest power consumption of all design candidates. The total power consumption saving compared to conventional array multiplier designs is up to 38.6%. The test chip measurement shows successful operations of our design down to 0.41 V with a power consumption of only 427 nW with a maximum frequency 500 KHz.

Low-Voltage Interface Technology for CGS TFT-LCD with Low Power Consumption

1999 ◽  
Vol 30 (1) ◽  
pp. 1116 ◽  
Author(s):  
Y. Kubota ◽  
H. Washio ◽  
K. Maeda ◽  
M. Hijikigawa ◽  
S. Yamazaki
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Voltage ◽  
Low Power Consumption
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