Analysis and Modeling of Imperfections in Multi-Bit Per Stage Pipelined ADCs

2016 ◽  
Vol 25 (07) ◽  
pp. 1650079 ◽  
Author(s):  
Najmeh Rahmani ◽  
Ebrahim Farshidi ◽  
Esmaeil Fatemi-Behbahani
Keyword(s):  
Signal To Noise Ratio ◽  
Significant Error ◽  
Pipelined Adc ◽  
Random Errors ◽  
Effective Number ◽  
Error Sources ◽  
Analog To Digital ◽  
Amplifier Output ◽  
Capacitor Mismatch ◽  
Pipelined Adcs

In this paper, an approach to estimate signal to noise ratio (SNR) and effective number of bits (ENOB) in nonideal multi-bit stages of pipelined analog to digital converters (ADCs) is presented. The most significant error sources in multistage ADCs are the capacitor mismatch and the finite and imprecise gain of amplifier. Output voltage of each stage in pipelined ADC is modeled by an ideal and a nonideal output, where nonideal output is the error due to circuit imperfections in each stage. Using an appropriate model, the SNR and ENOB due to circuit nonidealities and in terms of standard deviation of random errors are calculated. Simulation results show the accuracy of the analytical proposed approach in estimation of SNR and ENOB in multi-bit per stage pipelined converters.

scholarly journals A 3GSps 12-bit Four-Channel Time-Interleaved Pipelined ADC in 40 nm CMOS Process

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1551 ◽  
Author(s):  
Jianwen Li ◽  
Xuan Guo ◽  
Jian Luan ◽  
Danyu Wu ◽  
Lei Zhou ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Cmos Process ◽  
Pipelined Adc ◽  
Least Significant Bit ◽  
Analog To Digital ◽  
Capacitor Mismatch ◽  
Gain Error ◽  
Spurious Free Dynamic Range ◽  
Time Interleaved ◽  
Free Dynamic

This paper presents a four-channel time-interleaved 3GSps 12-bit pipelined analog-to-digital converter (ADC). The combination of master clock sampling and delay-adjusting is adopted to remove the time skew due to channel mismatches. An early comparison scheme is used to minimize the non-overlapping time, where a custom-designed latch is developed to replace the typical non-overlapping clock generator. By using the dither capacitor to generate an equivalent direct current input, a zero-input-based calibration is developed to correct the capacitor mismatch and inter-stage gain error. Fabricated in a 40 nm CMOS process, the ADC achieves a signal-to-noise-and-distortion ratio (SNDR) of 57.8 dB and a spurious free dynamic range (SFDR) of 72 dB with a 23 MHz input tone. It can achieve an SNDR above 52.3 dB and an SFDR above 61.5 dB across the entire first Nyquist zone. The differential and integral nonlinearities are −0.93/+0.73 least significant bit (LSB) and −2.8/+4.3 LSB, respectively. The ADC consumes 450 mW powered at 1.8V, occupies an active area of 3 mm × 1.3 mm. The calculated Walden figure of merit reaches 0.44 pJ/step.

scholarly journals A 10-bit 150MS/s Pipelined ADC with 2.5bit Gain Stage for High Frequency Applications

2019 ◽  
Vol 8 (10) ◽  
pp. 883-886
Keyword(s):  
Power Supply ◽  
High Frequency ◽  
Sampling Rate ◽  
High Accuracy ◽  
Pipelined Adc ◽  
Effective Number ◽  
Digital Converter ◽  
Analog To Digital ◽  
Computational Burden ◽  
Gain Stage

This paper proposes a 10-bit pipelined Analog to Digital Converter (ADC) which incorporates various techniques for lesser power and higher performance. The proposed method reduces the computational burden while comparing to the modified Monte-Carlo (MC) method. Pipelined ADC has N number of stages, it has higher resolution and higher frequency of conversion while comparing to other ADCs. The proposed ADC employs five 2.5bit gain stages; instead of 1.5bit gain stages for high accuracy. This method is implemented in the Tanner Software with the Generic 250nm library at a maximum power supply of 5V. The maximum frequency attained is 150MHz; and the ADC exhibits a SNR of 61.96dB. It also attains a 10bits as effective number of bits at the maximum sampling rate.

CONTRIBUTION TO THE ANALYSIS AND MODELING OF THE NON-IDEAL EFFECTS OF PIPELINED ADCs USING MATLAB

2013 ◽  
Vol 22 (02) ◽  
pp. 1250085 ◽  
Author(s):  
SAMIR BARRA ◽  
ABDELGHANI DENDOUGA ◽  
SOUHIL KOUDA ◽  
NOUR-EDDINE BOUGUECHAL
Keyword(s):  
Nonlinear Effects ◽  
Cmos Technology ◽  
Pipelined Adc ◽  
Data Converter ◽  
Analog To Digital ◽  
Op Amps ◽  
Pipelined Adcs ◽  
Pipeline Adcs ◽  
Improved Model ◽  
Basic Blocks

The present work analyses the non-ideal effects of pipelined analog-to-digital converters (ADCs), also sometimes referred to as pipeline ADCs, including the non-ideal effects in operational amplifiers (op-amps or OAs), switches and sampling circuits. We study these nonlinear effects in pipelined ADCs built using CMOS technology and switched-capacitor (SC) techniques. The proposed improved model of a pipelined ADC includes most of the non-idealities which affect its performance. This model, simulated using MATLAB, can determine the basic blocks specifications that allow the designer to meet given data converter requirements.

A DITHERING TECHNIQUE FOR SHA_LESS PIPELINED ADC

2014 ◽  
Vol 23 (01) ◽  
pp. 1450006 ◽  
Author(s):  
NING NING ◽  
LING DU ◽  
HUA CHEN ◽  
SHUANGYI WU ◽  
QI YU ◽  
...  
Keyword(s):  
Dynamic Range ◽  
Signal To Noise Ratio ◽  
Input Voltage ◽  
Pipelined Adc ◽  
Digital To Analog Converter ◽  
Analog To Digital ◽  
Behavior Simulation ◽  
Spurious Free Dynamic Range ◽  
Analog Converter ◽  
Free Dynamic

A dithering technique for pipelined analog-to-digital converter (ADC) without sample-and-hold amplifier (SHA) is proposed in this paper. The dither signals are injected to the output of the first stage multiplying digital-to-analog converter (MDAC) and the input of the first stage Sub_ADC simultaneously. The equivalent input voltage of the first stage Sub_ADC is consistent with that of the first stage MDAC with dither. To subtract the dither signal precisely, all of the dither signals are quantified by the ADC itself before normal conversion, and the digital codes representing dither signals are stored. During normal conversion, a dither signal selected randomly is added to the analog input and the corresponding digital code is subtracted from the digital output. The proposed dithering technique is verified by behavior simulation. The simulation results show that the spurious free dynamic range (SFDR) is improved effectively and the degradation of signal-to-noise ratio (SNR) can be minimized.

scholarly journals An Optical Analog-to-Digital Converter with Enhanced ENOB Based on MMI-Based Phase-Shift Quantization

Photonics ◽  
2021 ◽  
Vol 8 (2) ◽  
pp. 52
Author(s):  
Yue Liu ◽  
Jifang Qiu ◽  
Chang Liu ◽  
Yan He ◽  
Ran Tao ◽  
...  
Keyword(s):  
Phase Shift ◽  
Multimode Interference ◽  
Analog To Digital Converter ◽  
Effective Number ◽  
Digital Converter ◽  
Analog To Digital ◽  
Mmi Coupler ◽  
Simulation Results ◽  
Optical Analog ◽  
Optical Quantization

An optical analog-to-digital converter (OADC) scheme with enhanced bit resolution by using a multimode interference (MMI) coupler as optical quantization is proposed. The mathematical simulation model was established to verify the feasibility and to investigate the robustness of the scheme. Simulation results show that 20 quantization levels (corresponding to 4.32 of effective number of bits (ENOB)) are realized by using only 6 channels, which indicates that the scheme requires much fewer quantization channels or modulators to realize the same amount of ENOB. The scheme is robust and potential for integration.

Study of Wireless Torque Measurement System Based on CC2500

2011 ◽  
Vol 383-390 ◽  
pp. 5300-5303
Author(s):  
Wei Liu ◽  
Xiao Jie Song ◽  
Wen Gang Chen
Keyword(s):  
Signal To Noise Ratio ◽  
Digital Data ◽  
Measuring System ◽  
Instrumentation Amplifier ◽  
Torque Sensor ◽  
Torque Measurement ◽  
Analog To Digital ◽  
Wireless Transceiver ◽  
Precision Measuring ◽  
Transmission Shaft

It’s very difficult to get high precision measuring result using contact torquemeter because of very low signal-to-noise ratio. To overcome this defect, a wireless torque measuring system is designed based on CC2500. This system uses strain gauge torque sensor to measure the surface principal stress of the transmission shaft, and get the maximum shearing stress, and then the torque that the transmission shaft bears. The weak output signal of torque sensor is magnified by the instrumentation amplifier AD623, and sent to the analog-to-digital convertor. These digital data are transmited to the portable receiving terminal by the wireless transceiver chip CC2500. The dynamic wireless torque measurement is realized by this system.

A High Bandwidth Sigma-Delta Modulator Applied in Micro-Gyroscope

2013 ◽  
Vol 562-565 ◽  
pp. 369-373 ◽  
Author(s):  
Qiang Fu ◽  
Wei Ping Chen ◽  
Song Chen ◽  
Peng Fei Wang ◽  
Xiao Wei Liu
Keyword(s):  
Signal To Noise Ratio ◽  
System Simulation ◽  
Sampling Frequency ◽  
Effective Number ◽  
Signal To Noise ◽  
Sigma Delta Modulator ◽  
Sigma Delta ◽  
High Bandwidth ◽  
Oversampling Ratio ◽  
Input Level

In this paper a fourth-order single-loop sigma-delta modulator applied in micro-gyroscope is designed. The modulator system chose the fully feedforword structure. The signal bandwidth is 200KHz, oversampling ratio is 64 and sampling frequency is 25.6MHz. By system simulation result in Matlab, the signal to noise ratio (SNR) is 92.3dB and effective number of bits (ENOB) is 15.03bits. The whole circuit of modulator is designed and simulated in Cadence Spectre. It is gotten that the SNR is 78.6dB and changes linearly with input level. When input level is bigger than -4dBFs, the modulator becomes overload.

scholarly journals Compressive Detection Using Sub-Nyquist Radars for Sparse Signals

2016 ◽  
Vol 2016 ◽  
pp. 1-7
Author(s):  
Ying Sun ◽  
Jianjun Huang ◽  
Jingxiong Huang ◽  
Li Kang ◽  
Li Lei ◽  
...  
Keyword(s):  
Signal To Noise Ratio ◽  
Computation Time ◽  
Detection Performance ◽  
High Signal ◽  
Sparse Signals ◽  
Ratio Test ◽  
Digital Conversion ◽  
Real Time Processing ◽  
Analog To Digital ◽  
Analog To Digital Conversion

This paper investigates the compression detection problem using sub-Nyquist radars, which is well suited to the scenario of high bandwidths in real-time processing because it would significantly reduce the computational burden and save power consumption and computation time. A compressive generalized likelihood ratio test (GLRT) detector for sparse signals is proposed for sub-Nyquist radars without ever reconstructing the signal involved. The performance of the compressive GLRT detector is analyzed and the theoretical bounds are presented. The compressive GLRT detection performance of sub-Nyquist radars is also compared to the traditional GLRT detection performance of conventional radars, which employ traditional analog-to-digital conversion (ADC) at Nyquist sampling rates. Simulation results demonstrate that the former can perform almost as well as the latter with a very small fraction of the number of measurements required by traditional detection in relatively high signal-to-noise ratio (SNR) cases.

VCO-BASED CONTINUOUS-TIME SIGMA DELTA ADC BASED ON A DUAL-VCO-QUANTIZER-LOOP STRUCTURE

2013 ◽  
Vol 22 (09) ◽  
pp. 1340013 ◽  
Author(s):  
Z. T. XU ◽  
X. L. ZHANG ◽  
J. Z. CHEN ◽  
S. G. HU ◽  
Q. YU ◽  
...  
Keyword(s):  
Continuous Time ◽  
Signal To Noise Ratio ◽  
Quantization Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Loop Structure ◽  
Signal To Noise ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Adc

This paper explores a continuous time (CT) sigma delta (ΣΔ) analog-to-digital converter (ADC) based on a dual-voltage-controlled oscillator (VCO)-quantizer-loop structure. A third-order filter is adopted to reduce quantization noise and VCO nonlinearity. Even-order harmonics of VCO are significantly reduced by the proposed dual-VCO-quantizer-loop structure. The prototype with 10 MHz bandwidth and 400 MHz clock rate is designed using a 0.18 μm RF CMOS process. Simulation results show that the signal-to-noise ratio and signal-to-noise distortion ratio (SNDR) are 76.9 and 76 dB, respectively, consuming 37 mA at 1.8 V. The key module of the ADC, which is a 4-bit VCO-based quantizer, can convert the voltage signal into a frequency signal and quantize the corresponding frequency to thermometer codes at 400 MS/s.

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