Towards an Optimized Architecture for Unified Binary Huff Curves

2017 ◽  
Vol 26 (11) ◽  
pp. 1750178 ◽  
Author(s):  
Atif Raza Jafri ◽  
Muhammad Najam ul Islam ◽  
Malik Imran ◽  
Muhammad Rashid
Keyword(s):  
High Throughput ◽  
Elliptic Curve Cryptography ◽  
Power Analysis ◽  
State Of The Art ◽  
Area Ratio ◽  
Optimal Scheduling ◽  
Side Channel ◽  
Pipelined Architecture ◽  
Work Up ◽  
Logic Unit

Applying unified formula while computing point addition and doubling provides immunity to Elliptic Curve Cryptography (ECC) against power analysis attacks (a type of side channel attack). One of the popular techniques providing this unifiedness is the Binary Huff Curves (BHC) which got attention in 2011. In this paper we are presenting highly optimized architectures to implement point multiplication (PM) on the standard NIST curves over [Formula: see text] and [Formula: see text] using BHC. To achieve a high throughput over area ratio, first of all, we have used a simplified arithmetic and logic unit. Secondly, we have reduced the time to compute PM through Double and Add algorithm. This is achieved by increasing the frequency of operation through a 2-stage pipelined architecture. The increase in clock cycles caused by consequent pipeline hazards is controlled through optimal scheduling of computations involved in PM. The synthesis results show that our designs can work up to a frequency of 377[Formula: see text]MHz on Xilinx Virtex 7 FPGA. Moreover, the overall throughput/area ratio achieved through the adopted approach is up to 20% higher while comparing with available state-of-the-art solutions.

scholarly journals AREEBA: An Area Efficient Binary Huff-Curve Architecture

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1490
Author(s):  
Asher Sajid ◽  
Muhammad Rashid ◽  
Sajjad Shaukat Jamal ◽  
Malik Imran ◽  
Saud S. Alotaibi ◽  
...  
Keyword(s):  
Elliptic Curve Cryptography ◽  
Power Analysis ◽  
State Of The Art ◽  
Power Analysis Attacks ◽  
Low Area ◽  
Gate Arrays ◽  
Asymmetric Cryptography ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Computational Resources

Elliptic curve cryptography is the most widely employed class of asymmetric cryptography algorithm. However, it is exposed to simple power analysis attacks due to the lack of unifiedness over point doubling and addition operations. The unified crypto systems such as Binary Edward, Hessian and Huff curves provide resistance against power analysis attacks. Furthermore, Huff curves are more secure than Edward and Hessian curves but require more computational resources. Therefore, this article has provided a low area hardware architecture for point multiplication computation of Binary Huff curves over GF(2163) and GF(2233). To achieve this, a segmented least significant digit multiplier for polynomial multiplications is proposed. In order to provide a realistic and reasonable comparison with state of the art solutions, the proposed architecture is modeled in Verilog and synthesized for different field programmable gate arrays. For Virtex-4, Virtex-5, Virtex-6, and Virtex-7 devices, the utilized hardware resources in terms of hardware slices over GF(2163) are 5302, 2412, 2982 and 3508, respectively. The corresponding achieved values over GF(2233) are 11,557, 10,065, 4370 and 4261, respectively. The reported low area values provide the acceptability of this work in area-constrained applications.

scholarly journals Accelerating organic solar cell material's discovery: high-throughput screening and big data

2021 ◽  
Author(s):  
Xabier Rodríguez-Martínez ◽  
Enrique Pascual-San-José ◽  
Mariano Campoy-Quiles
Keyword(s):  
Machine Learning ◽  
Big Data ◽  
High Throughput ◽  
Organic Solar Cells ◽  
High Throughput Screening ◽  
Organic Solar Cell ◽  
State Of The Art ◽  
Review Article ◽  
Machine Learning Algorithms ◽  
Device Optimization

This review article presents the state-of-the-art in high-throughput computational and experimental screening routines with application in organic solar cells, including materials discovery, device optimization and machine-learning algorithms.

scholarly journals A secure and highly efficient first-order masking scheme for AES linear operations

Cybersecurity ◽  
2021 ◽  
Vol 4 (1) ◽  
Author(s):  
Jingdian Ming ◽  
Yongbin Zhou ◽  
Huizhong Li ◽  
Qian Zhang
Keyword(s):  
Cost Reduction ◽  
Provable Security ◽  
State Of The Art ◽  
Side Channel ◽  
First Order ◽  
Highly Efficient ◽  
Non Linear ◽  
Device Independence ◽  
Practical Implications ◽  
Provably Secure

AbstractDue to its provable security and remarkable device-independence, masking has been widely accepted as a noteworthy algorithmic-level countermeasure against side-channel attacks. However, relatively high cost of masking severely limits its applicability. Considering the high tackling complexity of non-linear operations, most masked AES implementations focus on the security and cost reduction of masked S-boxes. In this paper, we focus on linear operations, which seems to be underestimated, on the contrary. Specifically, we discover some security flaws and redundant processes in popular first-order masked AES linear operations, and pinpoint the underlying root causes. Then we propose a provably secure and highly efficient masking scheme for AES linear operations. In order to show its practical implications, we replace the linear operations of state-of-the-art first-order AES masking schemes with our proposal, while keeping their original non-linear operations unchanged. We implement four newly combined masking schemes on an Intel Core i7-4790 CPU, and the results show they are roughly 20% faster than those original ones. Then we select one masked implementation named RSMv2 due to its popularity, and investigate its security and efficiency on an AVR ATMega163 processor and four different FPGA devices. The results show that no exploitable first-order side-channel leakages are detected. Moreover, compared with original masked AES implementations, our combined approach is nearly 25% faster on the AVR processor, and at least 70% more efficient on four FPGA devices.

scholarly journals Reconfigurable Binary Neural Network Accelerator with Adaptive Parallelism Scheme

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 230
Author(s):  
Jaechan Cho ◽  
Yongchul Jung ◽  
Seongjoo Lee ◽  
Yunho Jung
Keyword(s):  
Neural Networks ◽  
High Throughput ◽  
Deep Neural Networks ◽  
State Of The Art ◽  
Throughput Performance ◽  
Adaptive Parallelism ◽  
Sensor Applications ◽  
Binary Neural Network ◽  
Target Layer ◽  
Network Topologies

Binary neural networks (BNNs) have attracted significant interest for the implementation of deep neural networks (DNNs) on resource-constrained edge devices, and various BNN accelerator architectures have been proposed to achieve higher efficiency. BNN accelerators can be divided into two categories: streaming and layer accelerators. Although streaming accelerators designed for a specific BNN network topology provide high throughput, they are infeasible for various sensor applications in edge AI because of their complexity and inflexibility. In contrast, layer accelerators with reasonable resources can support various network topologies, but they operate with the same parallelism for all the layers of the BNN, which degrades throughput performance at certain layers. To overcome this problem, we propose a BNN accelerator with adaptive parallelism that offers high throughput performance in all layers. The proposed accelerator analyzes target layer parameters and operates with optimal parallelism using reasonable resources. In addition, this architecture is able to fully compute all types of BNN layers thanks to its reconfigurability, and it can achieve a higher area–speed efficiency than existing accelerators. In performance evaluation using state-of-the-art BNN topologies, the designed BNN accelerator achieved an area–speed efficiency 9.69 times higher than previous FPGA implementations and 24% higher than existing VLSI implementations for BNNs.

A High-Throughput Architecture for the SHA-256/224 Compliant With the DSRC Standard

2019 ◽  
Vol 10 (1) ◽  
pp. 98-118
Author(s):  
Imed Saad Ben Dhaou ◽  
Hannu Tenhunen
Keyword(s):  
High Throughput ◽  
Short Range ◽  
State Of The Art ◽  
High Level Synthesis ◽  
Data Flow Graph ◽  
Transformation Techniques ◽  
Safety Message ◽  
Dedicated Short Range Communication ◽  
Field Programmable ◽  
High Level

This article presents a word serial retimed architecture for the SHA-256/224 algorithm. The architecture is compliant with the dedicated-short range communication for safety message authentications. We elaborate three-operand adder architectures suitable for field programmable gate array implementation. Several transformation techniques at the data-flow-graph level have been used to derive the architecture. Synthesis results show that the architecture has high throughput/ slice value compared with state-of-the-art SHA-256 implementations. The article also promulgates a comparison between high-level synthesis and RTL design.

scholarly journals Side-Channel Power Resistance for Encryption Algorithms Using Implementation Diversity

Cryptography ◽  
2020 ◽  
Vol 4 (2) ◽  
pp. 13
Author(s):  
Ivan Bow ◽  
Nahome Bete ◽  
Fareena Saqib ◽  
Wenjie Che ◽  
Chintan Patel ◽  
...  
Keyword(s):  
Power Analysis ◽  
Side Channel ◽  
Side Channel Attacks ◽  
Dynamic Partial Reconfiguration ◽  
Channel Power ◽  
Diversity Techniques ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Encryption Algorithms

This paper investigates countermeasures to side-channel attacks. A dynamic partial reconfiguration (DPR) method is proposed for field programmable gate arrays (FPGAs)s to make techniques such as differential power analysis (DPA) and correlation power analysis (CPA) difficult and ineffective. We call the technique side-channel power resistance for encryption algorithms using DPR, or SPREAD. SPREAD is designed to reduce cryptographic key related signal correlations in power supply transients by changing components of the hardware implementation on-the-fly using DPR. Replicated primitives within the advanced encryption standard (AES) algorithm, in particular, the substitution-box (SBOX)s, are synthesized to multiple and distinct gate-level implementations. The different implementations change the delay characteristics of the SBOXs, reducing correlations in the power traces, which, in turn, increases the difficulty of side-channel attacks. The effectiveness of the proposed countermeasures depends greatly on this principle; therefore, the focus of this paper is on the evaluation of implementation diversity techniques.

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