Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure

2017 ◽  
Vol 26 (12) ◽  
pp. 1750197 ◽  
Author(s):  
Fatemeh Abdi ◽  
Mahnaz Janipoor Deylamani ◽  
Parviz Amiri
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Input Voltage ◽  
Bias Current ◽  
Cmos Process ◽  
Slew Rate ◽  
Load Current ◽  
Rate Enhancement ◽  
Error Amplifier ◽  
Response Enhancement

In this paper, we use bias current boosting and slew rate enhancement in multiple-output Low-dropout structure to achieve a faster transient response. This method reduces ripples of output voltage during sudden changes in load current and input voltage. The proposed MOLDO circuit was simulated with a 0.18[Formula: see text][Formula: see text]m CMOS process in buck mode with four-output legs. Integrating of proposed circuit is easier because there is the symmetry in the circuit designing. The results of our work show that when input voltage changes between 2.5–3.3[Formula: see text]V, the output voltage after 25[Formula: see text][Formula: see text]s with load current of 100[Formula: see text]mA, is determined with ripple less than 1.8[Formula: see text]mV. In sudden changes, the load current at the range 0–100[Formula: see text]mA, and output voltages after a maximum 15.5[Formula: see text][Formula: see text]s with an input voltage of 3.3[Formula: see text]V have the highest ripple in output voltage of 4[Formula: see text]mV.

A Three-Stage Coarse-Fine-Tuning Analog-Assisted Digital LDO

2020 ◽  
pp. 2150047
Author(s):  
Lianxi Liu ◽  
Yiwei Chen ◽  
Xufeng Liao ◽  
Junchao Mu ◽  
Yintang Yang
Keyword(s):  
Output Voltage ◽  
Maximum Load ◽  
Input Voltage ◽  
Fine Tuning ◽  
Cmos Process ◽  
Load Current ◽  
Input Range ◽  
Low Dropout Regulator ◽  
Layout Area ◽  
Two Stages

This paper proposes a three-stage coarse-fine-tuning analog-assisted digital low dropout regulator (AAD-LDO) without digital ripple. The digital regulation consists of two stages, which break the accuracy-speed-power trade-off. To further improve transient response, a step-variable counter used in the first stage is designed, which makes sure that the output current can track the load current rapidly. The ripple caused by the digital regulation disappears due to the existence of the analog-assistant stage (in the proposed AAD-LDO). As a result, the AAD-LDO achieves the output voltage with high accuracy. Designed in a 0.18[Formula: see text][Formula: see text]m CMOS process, the proposed AAD-LDO has a layout area of 0.133[Formula: see text]mm. For the input range of 1.2–1.8[Formula: see text]V, the output voltage is 1[Formula: see text]V. The maximum load current is 10[Formula: see text]mA at the input voltage of 1.2[Formula: see text]V. The linear regulation and load regulation are 0.061[Formula: see text]mV/V and 0.0082[Formula: see text]mV/mA, respectively. The over/undershoot is suppressed effectively for a 9.5[Formula: see text]mA load step. The peak current efficiency is 99.78%.

Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure

2019 ◽  
Vol 28 (09) ◽  
pp. 1992001
Author(s):  
Fatemeh Abdi ◽  
Mahnaz Janipoor Deylamani ◽  
Parviz Amiri ◽  
Mohammad Hossein Refan
Keyword(s):  
Transient Response ◽  
Slew Rate ◽  
Error Amplifier ◽  
Response Enhancement

Transient Response Enhancement with Fast Transient Controller for Capacitor-Less LDO Regulator

2014 ◽  
Vol 543-547 ◽  
pp. 800-805 ◽  
Author(s):  
Shang Sheng Chi ◽  
Wei Hu ◽  
Ming Hui Fan ◽  
Yu Sen Xu ◽  
Guo Lin Chen
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Input Voltage ◽  
Settling Time ◽  
Voltage Range ◽  
Class Ab ◽  
Response Enhancement ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Ldo Regulator

This paper presents a capacitor-less CMOS low dropout regulator (LDO) with a push-pull class AB amplifier, and a fast transient controller to achieve a better transient response. The undershoot/overshoot voltage and the settling time are effectively reduced. Through the theoretical analysis of the circuit, cadence simulation with SMIC 0.18μm process and under the condition of the input voltage range 1.4~4 V shows the output voltage is 1.2 V, with the fast controller the total quiescent current is 8.2 μA, the undershoot /overshoot voltage is 97 mV/47 mV and the settling time is 0.3 μs as load current suddenly changes from 1 to 100 mA, or vice versa. Compared with this paper without fast transient controller, the undershoot voltage, the overshoot voltage and the settling time are enhanced by 30%, 64% and 80%, respectively.

A HIGH EFFICIENCY ADAPTIVE CURRENT MODE STEP-UP/STEP-DOWN DC–DC CONVERTER WITH FOUR MODES FOR SMOOTH TRANSITION

2014 ◽  
Vol 23 (07) ◽  
pp. 1450097 ◽  
Author(s):  
YANZHAO MA ◽  
SHAOXI WANG ◽  
SHENGBING ZHANG ◽  
XIAOYA FAN
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
High Efficiency ◽  
Current Mode ◽  
Smooth Transition ◽  
Maximum Efficiency ◽  
Cmos Process ◽  
Voltage Ripple ◽  
Transition Modes ◽  
Step Down

This paper presents a current mode step-up/step-down DC–DC converter with high efficiency, small output voltage ripple, and fast transient response. The control scheme adaptively configures the converter into the proper operation mode. The efficiency is improved by reducing the switching loss, wherein the converter operates like a buck or boost converter, and conduction loss, wherein the average inductor current is reduced in transition modes. The output voltage ripple is significantly reduced by incorporating two constant time transition modes. A fast line transient response is achieved with small overshoot and undershoot voltage. An adaptive substrate selector (ASS) is introduced to dynamically switch the substrate of PMOS power transistors to the highest on-chip voltage. A lossless self-biased current sensor with high-speed and high-accuracy is also achieved. The proposed converter was designed with a standard 0.5 μm CMOS process, and can regulate an output voltage within the input voltage ranged from 2.5 V to 5.5 V. The maximum load current is 600 mA, and the maximum efficiency is 94%. The output voltage ripple is less than 15 mV in all operation modes.

Fuzzy Gain Scheduling of PI Plus Derivative Controller to Improve the Transient Response of Boost DC/DC Converter

2015 ◽  
Vol 781 ◽  
pp. 414-417
Author(s):  
Yutthana Kanthaphayao ◽  
Chalermpol Reaungepattanawiwat
Keyword(s):  
Control System ◽  
Steady State ◽  
Transient Response ◽  
Output Voltage ◽  
Input Voltage ◽  
Gain Scheduling ◽  
Voltage Regulation ◽  
Control Technique ◽  
Transient Responses ◽  
System Operation

This paper illustrates a fuzzy gain scheduling of PI plus derivative controller. The proposed control technique improves the transient response of a DC/DC converter. The proposed control system is easy to implement based on an STM32F4 microcontroller. The performance evaluation was done by an experiment through a boost DC/DC converter, with a 24W load, a 12V input voltage, and a 24V output voltage, respectively. The system operation achieves tight output voltage regulation, both for the steady-state and transient responses.

Fast-Transient-Response Low-Voltage Integrated, Interleaved DC–DC Converter for Implantable Devices

2019 ◽  
Vol 29 (01) ◽  
pp. 2050013
Author(s):  
Najmeh Cheraghi Shirazi ◽  
Abumoslem Jannesari ◽  
Pooya Torkzadeh
Keyword(s):  
Power Consumption ◽  
Transient Response ◽  
Output Voltage ◽  
Low Voltage ◽  
Charge Pump ◽  
Input Voltage ◽  
Cmos Technology ◽  
Clock Frequency ◽  
Voltage Ripple ◽  
Body Biasing

A new self-start-up switched-capacitor charge pump is proposed for low-power, low-voltage and battery-less implantable applications. To minimize output voltage ripple and improve transient response, interleaving regulation technique is applied to a multi-stage Cross-Coupled Charge Pump (CCCP) circuit. It splits the power flow in a time-sequenced manner. Three cases of study are designed and investigated with body-biasing technique by auxiliary transistors: Four-stage Two-Branch CCCP (TBCCCP), the two-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP2) and four-cell four-stage Interleaved Two-Branch CCCP (ITBCCCP4). Multi-phase nonoverlap clock generator circuit with body-biasing technique is also proposed which can operate at voltages as low as CCCP circuits. The proposed circuits are designed with input voltage as low as 300 to 400[Formula: see text]mV and 20[Formula: see text]MHz clock frequency for 1[Formula: see text]pF load capacitance. Among the three designs, ITBCCCP4 has the lowest ramp-up time (41.6% faster), output voltage ripple (29% less) and power consumption (19% less). The Figure-Of-Merit (FOM) of ITBCCCP4 is the highest value among two others. For 400[Formula: see text]mV input voltage, ITBCCCP4 has a 98.3% pumping efficiency within 11.6[Formula: see text][Formula: see text]s, while having a maximum voltage ripple of 0.1% and a power consumption as low as 2.7[Formula: see text]nW. The FOM is 0.66 for this circuit. The designed circuits are implemented in 180-nm standard CMOS technology with an effective chip area of [Formula: see text][Formula: see text][Formula: see text]m for TBCCCP, [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP2 and [Formula: see text][Formula: see text][Formula: see text]m for ITBCCCP4.

A LOW POWER CURRENT RECYCLING CONSTANT-gm RAIL-TO-RAIL OTA

2014 ◽  
Vol 23 (02) ◽  
pp. 1450022
Author(s):  
XIAO ZHAO ◽  
HUAJUN FANG ◽  
JUN XU
Keyword(s):  
Low Power ◽  
Bias Current ◽  
Cmos Process ◽  
Slew Rate ◽  
Gain Bandwidth ◽  
Design Specifications ◽  
Rail To Rail ◽  
Dc Gain ◽  
Unity Gain ◽  
Simulation Results

A low power current recycling constant-gm rail-to-rail (RtR) OTA is presented. The proposed amplifier has the benefit of delivering the same performance while consuming half the power compared to the conventional RtR amplifier. This is achieved by recycling the bias current of idle devices, which results in an enhanced transconductance, gain and slew rate. The proposed amplifier was implemented in CSMC standard 0.18 um CMOS process. Simulation results show that the proposed amplifier achieves 10.2 MHz unity-gain bandwidth, 59.4 dB DC gain, 4.8 V/us slew rate and less than 8% deviation in transconductance, but the power consumption reduced by 50% compared to the conventional RtR amplifier with the same design specifications.

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