A Three-Stage Coarse-Fine-Tuning Analog-Assisted Digital LDO

2020 ◽  
pp. 2150047
Author(s):  
Lianxi Liu ◽  
Yiwei Chen ◽  
Xufeng Liao ◽  
Junchao Mu ◽  
Yintang Yang
Keyword(s):  
Output Voltage ◽  
Maximum Load ◽  
Input Voltage ◽  
Fine Tuning ◽  
Cmos Process ◽  
Load Current ◽  
Input Range ◽  
Low Dropout Regulator ◽  
Layout Area ◽  
Two Stages

This paper proposes a three-stage coarse-fine-tuning analog-assisted digital low dropout regulator (AAD-LDO) without digital ripple. The digital regulation consists of two stages, which break the accuracy-speed-power trade-off. To further improve transient response, a step-variable counter used in the first stage is designed, which makes sure that the output current can track the load current rapidly. The ripple caused by the digital regulation disappears due to the existence of the analog-assistant stage (in the proposed AAD-LDO). As a result, the AAD-LDO achieves the output voltage with high accuracy. Designed in a 0.18[Formula: see text][Formula: see text]m CMOS process, the proposed AAD-LDO has a layout area of 0.133[Formula: see text]mm. For the input range of 1.2–1.8[Formula: see text]V, the output voltage is 1[Formula: see text]V. The maximum load current is 10[Formula: see text]mA at the input voltage of 1.2[Formula: see text]V. The linear regulation and load regulation are 0.061[Formula: see text]mV/V and 0.0082[Formula: see text]mV/mA, respectively. The over/undershoot is suppressed effectively for a 9.5[Formula: see text]mA load step. The peak current efficiency is 99.78%.

Slew Rate and Transient Response Enhancement in MOLDO with Modifying Error Amplifier Structure

2017 ◽  
Vol 26 (12) ◽  
pp. 1750197 ◽  
Author(s):  
Fatemeh Abdi ◽  
Mahnaz Janipoor Deylamani ◽  
Parviz Amiri
Keyword(s):  
Transient Response ◽  
Output Voltage ◽  
Input Voltage ◽  
Bias Current ◽  
Cmos Process ◽  
Slew Rate ◽  
Load Current ◽  
Rate Enhancement ◽  
Error Amplifier ◽  
Response Enhancement

In this paper, we use bias current boosting and slew rate enhancement in multiple-output Low-dropout structure to achieve a faster transient response. This method reduces ripples of output voltage during sudden changes in load current and input voltage. The proposed MOLDO circuit was simulated with a 0.18[Formula: see text][Formula: see text]m CMOS process in buck mode with four-output legs. Integrating of proposed circuit is easier because there is the symmetry in the circuit designing. The results of our work show that when input voltage changes between 2.5–3.3[Formula: see text]V, the output voltage after 25[Formula: see text][Formula: see text]s with load current of 100[Formula: see text]mA, is determined with ripple less than 1.8[Formula: see text]mV. In sudden changes, the load current at the range 0–100[Formula: see text]mA, and output voltages after a maximum 15.5[Formula: see text][Formula: see text]s with an input voltage of 3.3[Formula: see text]V have the highest ripple in output voltage of 4[Formula: see text]mV.

Fast Transient Capacitor-Less Low-Dropout Regulator Based on Output Voltage Spike Reduction Circuits for SOC Applications

2019 ◽  
Vol 28 (03) ◽  
pp. 1950043 ◽  
Author(s):  
M. Jahangiri ◽  
A. Farrokhi
Keyword(s):  
Output Voltage ◽  
Input Voltage ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Wide Range ◽  
Unity Gain ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
On Chip ◽  
Voltage Spike

A fast transient capacitor-less low-dropout regulator is presented in this study. The proposed LDO structure is based on Output Voltage Spike Reduction (OVSR) circuits and capacitance compensation circuits to enable a fast-transient response with ultra-low power dissipation and to make the LDO stable for a wide range of output load currents (0–50[Formula: see text]mA). The slew rate is improved with more slew current from the OVSR circuit and unity gain bandwidth is improved by a capacitor multiplayer circuit. The proposed LDO has been simulated with a standard 0.18[Formula: see text][Formula: see text]m CMOS process. The output voltage of the LDO was set to 1.2[Formula: see text]V for an input voltage of 1.4–2[Formula: see text]V. The Simulation results verify that the transient times are less than 2.8[Formula: see text][Formula: see text]s and the maximum undershoot and overshoot are 20[Formula: see text]mV while consuming only 26[Formula: see text][Formula: see text]A quiescent current. The proposed LDO is stable with an on-chip capacitor at the output node within the wide range of 1100[Formula: see text]PF.

scholarly journals An Output Capacitor-Less Low-Dropout Regulator with 0–100 mA Wide Load Current Range

Energies ◽  
2019 ◽  
Vol 12 (2) ◽  
pp. 211 ◽  
Author(s):  
Jihoon Park ◽  
Woong-Joon Ko ◽  
Dong-Seok Kang ◽  
Yoonmyung Lee ◽  
Jung-Hoon Chun
Keyword(s):  
Cmos Process ◽  
Load Current ◽  
Flipped Voltage Follower ◽  
Better Regulation ◽  
Wide Range ◽  
Voltage Follower ◽  
Low Dropout Regulator ◽  
Output Capacitor ◽  
Ldo Regulator ◽  
Two Stages

An output capacitor-less low-dropout (OCL-LDO) regulator with a wide range of load currents is proposed in this study. The structure of the proposed regulator is based on the flipped-voltage-follower LDO regulator. The feedback loop of the proposed regulator consists of two stages. The second stage is turned on or off depending on the variation in the output load current. Hence, the regulator can retain a phase margin at a wide range of load currents. The proposed regulator exhibits a better regulation performance compared to the ones in previous studies. The test chip is fabricated using a 65-nm CMOS process.

A Sub-1V 0.18um Output-Capacitor-Free Digitally Controlled LDO

2015 ◽  
Vol 764-765 ◽  
pp. 471-475 ◽  
Author(s):  
Wei Bin Yang ◽  
Shao Jyun Xie ◽  
Han Hsien Wang
Keyword(s):  
Current Efficiency ◽  
Operational Amplifier ◽  
Output Voltage ◽  
Input Voltage ◽  
Control Loop ◽  
Load Current ◽  
Digitally Controlled ◽  
Quiescent Current ◽  
Low Dropout Regulator ◽  
Output Capacitor

The new digital control loop of the low-dropout regulator (LDO) is presented. It is composed of coarse tracking circuit and fine tracking circuit, and no external output capacitor is required to stabilize the control loop. The proposed method makes the quiescent current lower than conventional analog LDOs. The operational amplifier of the conventional LDO fails to operate at 0.7V, and the developed digital LDO in 0.18um CMOS achieved the 0.7V input voltage and 0.5V output voltage with 99.99% current efficiency and 2.6-μA quiescent current at 20mA load current. Therefore, the proposed DLDO is suitable for low power applications.

scholarly journals A Low-Dropout Regulator with PSRR Enhancement through Feed-Forward Ripple Cancellation Technique in 65 nm CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 146
Author(s):  
Young-Joe Choe ◽  
Hyohyun Nam ◽  
Jung-Dong Park
Keyword(s):  
Maximum Load ◽  
Input Voltage ◽  
Cmos Technology ◽  
Cmos Process ◽  
Feed Forward ◽  
Power Supply Rejection Ratio ◽  
Wide Range ◽  
Low Dropout Regulator ◽  
Ldo Regulator ◽  
Ripple Cancellation

In this paper, a low-dropout (LDO) regulator with an enhanced power supply rejection ratio (PSRR) is proposed with a feed-forward ripple cancellation technique (FFRC) in 65 nm CMOS technology. This technique significantly improves the PSRR over a wide range of frequencies, compared to a conventional LDO regulator. The LDO regulator provides 35–76.8 dB of PSRR in the range of 1 MHz–1 GHz, which shows up to 30 dB of PSRR improvement, compared with that of the conventional LDO regulator. The implemented LDO regulator has a dropout voltage of 0.22 V and a maximum load current of 20 mA. It can also provide an output voltage of 0.98 V at a range of 1–1.3 V of the input voltage. The load regulation is 2.3 mV/mA while the line regulation is 0.05 V/V. The circuit consumes 385 μA with an input voltage of 1.2 V. The total area without pads is 0.092 mm2.

Self-Reduction Quiescent Current Low Power Low Dropout Regulator for SoC Application

2012 ◽  
Vol 591-593 ◽  
pp. 2632-2635
Author(s):  
Lee Chu Liang ◽  
Roslina Mohd Sidek
Keyword(s):  
Low Power ◽  
Process Model ◽  
High Efficiency ◽  
System Stability ◽  
Cmos Process ◽  
Output Impedance ◽  
Load Current ◽  
Output Load ◽  
Quiescent Current ◽  
Low Dropout Regulator

A low power low-dropout (LDO) voltage regulator with self-reduction quiescent current is proposed in this paper. This proposed capacitorless LDO for Silicon-on-Chip (SoC) application has introduced a self-adjustable low-impedance circuitry at the output of LDO to attain stability critically during low output load current (less than a few hundred of micro-ampere). When the LDO load current increases, it reduces the LDO output impedance and moved the pole towards higher frequency away from the dominant pole and improving the system stability. When this happen, less amount of quiescent current is needed for the low-impedance circuitry to sustain the low output impedance. In this proposed LDO, the quiescent current that been used to sustain the low output impedance will be self-reduced when the output load current increases. Thus, the reduction of quiescent current at low output load current has tremendously improved the efficiency. The simulation results have shown a promising stability at low load current 0~1mA. The dropout voltage for this LDO is only 100mV at 1.2V supply. The proposed LDO is validated using Silterra 0.13μm CMOS process model and designed with high efficiency at low output load current.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

scholarly journals Design of a Low-Noise, Fast Set-up and Low-Voltage Low-Dropout Regulator Featuring 230mA Load Current Range

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Low Voltage ◽  
Input Voltage ◽  
Low Noise ◽  
Cmos Process ◽  
Transient Time ◽  
Voltage Range ◽  
Fast Transient ◽  
Low Dropout Regulator ◽  
Set Up ◽  
Ldo Regulator

Low noise, high PSRR and fast transient low-dropout (LDO) regulators are critical for analog blocks such as ADCs, PLLs and RF SOC, etc. This paper presents design of low power, fast transient, high PSRR and high load-regulation low-dropout (LDO) regulator. The proposed LDO regulator is designed in 180nm. CMOS process and simulated in LTSpice and Cadence platform. The LDO proposed can support input voltage range up to 5V for loading currents up to 230mA. Measurements showed transient time or set-up time of less than 22µs, PSRR of ~66dB at 100kHz and >40dB at 1MHz and 0.8535mV of output voltage variation for a 0-230mA of load variation.

scholarly journals Proposal and design methodology of switching mode low dropout regulator for Bio-medical applications

2019 ◽  
Vol 9 (6) ◽  
pp. 5046
Author(s):  
Kenya Kondo ◽  
Hiroki Tamura ◽  
Koichi Tanno
Keyword(s):  
Low Frequency ◽  
Design Procedure ◽  
Logic Gates ◽  
Maximum Load ◽  
Cmos Process ◽  
Light Load ◽  
Analog Front End ◽  
Low Dropout Regulator ◽  
Switching Mode ◽  
Ldo Regulator

<p>The switching operation based low dropout (LDO) regulator utilizing on-off control is pre-sented. It consists of simple circuit elements which are comparator, some logic gates, switched capacitor and feedback circuit. In this study, we target the application to the power supply circuit for the analog front end (AFE) of bio-medical system (such as daily-used bio-monitoring devices) whose required maximum load current is 50 A. In this paper, the design procedure of the proposed LDO has been clarified and actual circuit design using the procedure has been done. The proposed LDO has been evaluated by SPICE simulation using 1P 2M 0.6 m CMOS process device parameters. From simulation results, we could confirm that the low quiescent current of 1 A with the output ripple of 5 mVpp. The circuit area is 0.0173 mm2 in spite of using 0.6 m design rules. The proposed circuit is suitable for adopting to the light load and low frequency applications.</p>

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