A Review on Calibration Methods of Timing-Skew in Time-Interleaved ADCs

2019 ◽  
Vol 29 (02) ◽  
pp. 2030002
Author(s):  
Xin Li ◽  
Cheng Huang ◽  
Desheng Ding ◽  
Jianhui Wu
Keyword(s):  
State Of The Art ◽  
Time Interleaving ◽  
Analog To Digital ◽  
Systematic Overview ◽  
Current State ◽  
Calibration Methods ◽  
Overall Performance ◽  
Time Interleaved ◽  
Statistical Results ◽  
Timing Skew

Time-interleaving has been a popular choice for multi-GHz analog-to-digital converters (ADCs) with a resolution of 8–14 bits. Unfortunately, inherent defects such as offset, gain, timing-skew mismatches among sub-ADCs degrade overall performance seriously. At present, the method for eliminating offset and gain mismatch is fairly straightforward; however, calibration for timing-skew is still in a state of exploration. A systematic overview of various calibration methods for timing-skew in time-interleaved ADCs (TI-ADCs) has been provided in this paper. Meanwhile, current state-of-the-art TI-ADCs recently are reported and several noteworthy trends can be observed from the statistical results.

scholarly journals Ensemble-Based Out-of-Distribution Detection

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 567
Author(s):  
Donghun Yang ◽  
Kien Mai Mai Ngoc ◽  
Iksoo Shin ◽  
Kyong-Ha Lee ◽  
Myunggwon Hwang
Keyword(s):  
Detection Method ◽  
State Of The Art ◽  
Metric Learning ◽  
Feature Space ◽  
Confidence Score ◽  
Distance Metric Learning ◽  
Current State ◽  
Overall Performance ◽  
Deep Learning Model

To design an efficient deep learning model that can be used in the real-world, it is important to detect out-of-distribution (OOD) data well. Various studies have been conducted to solve the OOD problem. The current state-of-the-art approach uses a confidence score based on the Mahalanobis distance in a feature space. Although it outperformed the previous approaches, the results were sensitive to the quality of the trained model and the dataset complexity. Herein, we propose a novel OOD detection method that can train more efficient feature space for OOD detection. The proposed method uses an ensemble of the features trained using the softmax-based classifier and the network based on distance metric learning (DML). Through the complementary interaction of these two networks, the trained feature space has a more clumped distribution and can fit well on the Gaussian distribution by class. Therefore, OOD data can be efficiently detected by setting a threshold in the trained feature space. To evaluate the proposed method, we applied our method to various combinations of image datasets. The results show that the overall performance of the proposed approach is superior to those of other methods, including the state-of-the-art approach, on any combination of datasets.

A Bandwidth Mismatch Optimization Technique in Time-Interleaved Analog-to-Digital Converters

2019 ◽  
Vol 28 (06) ◽  
pp. 1950090
Author(s):  
Jian Luo ◽  
Jing Li ◽  
Shuangyi Wu ◽  
Ning Ning ◽  
Yang Liu
Keyword(s):  
Simulated Annealing Algorithm ◽  
Dynamic Range ◽  
Optimization Technique ◽  
Analog To Digital Converters ◽  
Analog To Digital ◽  
Limited Bandwidth ◽  
Behavior Simulation ◽  
Calibration Methods ◽  
Time Interleaved ◽  
Sampling Sequences

In time-interleaved (TI) analog-to-digital converters (ADCs), bandwidth mismatches, caused by the limited bandwidth of input signal traces and sample circuits, seriously deteriorate the spurious-free dynamic range (SFDR) of the system. This paper analyzes the influence of bandwidth mismatch errors under different sampling sequences. Eventually, based on a randomization technique and the simulated annealing algorithm (SAA), a bandwidth mismatch optimization technique is presented that can work well with other bandwidth mismatch calibration methods. The behavior simulation results indicate that an improvement of 7[Formula: see text]dB in the SFDR can be achieved with this technique in a 16-channel TI-ADC after timing and gain calibration.

A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS

2020 ◽  
pp. 2150143
Author(s):  
Lei Zhao ◽  
Dengquan Li ◽  
Henghui Mao ◽  
Ruixue Ding ◽  
Zhangming Zhu
Keyword(s):  
Power Efficiency ◽  
State Of The Art ◽  
Signal To Noise Ratio ◽  
Analog To Digital ◽  
Clock Feedthrough ◽  
Second Stage ◽  
Front End ◽  
Simulation Results ◽  
Good Trade ◽  
Time Interleaved

This paper presents a 32-GS/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the [Formula: see text] two-stage interleaving structure leads to a good trade-off between bandwidth and linearity. The analysis and cancellation of charge injection, clock feedthrough, and signal feedthrough are presented. Inductor peaking technique is adopted to extend the bandwidth of the buffer between the first and the second stage. Based on the simulation results, the proposed FESC consumes 136[Formula: see text]mW at 32 GS/s, and the signal-to-noise ratio (SNDR) is up to 39.55 dB at Nyquist input, achieving a state-of-the-art power efficiency.

An adaptive calibration technique of timing skew mismatch in time-interleaved analog-to-digital converters

2019 ◽  
Vol 90 (2) ◽  
pp. 025102 ◽  
Author(s):  
Jian Gao ◽  
Peng Ye ◽  
Hao Zeng ◽  
Jinpeng Song ◽  
Wentao Wei ◽  
...  
Keyword(s):  
Analog To Digital Converters ◽  
Calibration Technique ◽  
Analog To Digital ◽  
Adaptive Calibration ◽  
Time Interleaved ◽  
Timing Skew

scholarly journals Calibration for Sample-And-Hold Mismatches in M-Channel TIADCs Based on Statistics

2019 ◽  
Vol 9 (1) ◽  
pp. 198 ◽  
Author(s):  
Xiangyu Liu ◽  
Hui Xu ◽  
Yinan Wang ◽  
Yingqiang Dai ◽  
Nan Li ◽  
...  
Keyword(s):  
Dynamic Performance ◽  
Sampling Rate ◽  
Analog To Digital ◽  
Sample And Hold ◽  
High Sampling Rate ◽  
Calibration Methods ◽  
Input Signals ◽  
Calibration Algorithm ◽  
Signal Simulation ◽  
Time Interleaved

Time-interleaved analog-to-digital converter (TIADC) is a good option for high sampling rate applications. However, the inevitable sample-and-hold (S/H) mismatches between channels incur undesirable error and then affect the TIADC’s dynamic performance. Several calibration methods have been proposed for S/H mismatches which either need training signals or have less extensive applicability for different input signals and different numbers of channels. This paper proposes a statistics-based calibration algorithm for S/H mismatches in M-channel TIADCs. Initially, the mismatch coefficients are identified by eliminating the statistical differences between channels. Subsequently, the mismatch-induced error is approximated by employing variable multipliers and differentiators in several Richardson iterations. Finally, the error is subtracted from the original output signal to approximate the expected signal. Simulation results illustrate the effectiveness of the proposed method, the selection of key parameters and the advantage to other methods.

HIGH-SPEED OVERSAMPLING ANALOG-TO-DIGITAL CONVERTERS

2005 ◽  
Vol 15 (02) ◽  
pp. 297-317 ◽  
Author(s):  
AHMED GHARBIYA ◽  
TREVOR C. CALDWELL ◽  
D. A. JOHNS
Keyword(s):  
Discrete Time ◽  
Input Signal ◽  
Continuous Time ◽  
High Frequency ◽  
High Speed ◽  
State Of The Art ◽  
Analog To Digital Converters ◽  
Analog To Digital ◽  
Time Interleaved

This paper is mainly tutorial in nature and discusses architectures for oversampling converters with a particular emphasis on those which are well suited for high frequency input signal bandwidths. The first part of the paper looks at various architectures for discrete-time modulators and looks at their performance when attempting high speed operation. The second part of this paper presents some recent advancements in time-interleaved oversampling converters. The next section describes the design and challenges in continuous-time modulators. Finally, conclusions are made and a brief summary of the recent state of the art of high-speed converters is presented.

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