A 32-GS/s Front-End Sampling Circuit Achieving >39 dB SNDR for Time-Interleaved ADCs in 65-nm CMOS

2020 ◽  
pp. 2150143
Author(s):  
Lei Zhao ◽  
Dengquan Li ◽  
Henghui Mao ◽  
Ruixue Ding ◽  
Zhangming Zhu
Keyword(s):  
Power Efficiency ◽  
State Of The Art ◽  
Signal To Noise Ratio ◽  
Analog To Digital ◽  
Clock Feedthrough ◽  
Second Stage ◽  
Front End ◽  
Simulation Results ◽  
Good Trade ◽  
Time Interleaved

This paper presents a 32-GS/s front-end sampling circuit (FESC) in 65-nm CMOS. The FESC is designed for a 32-channel time-interleaved analog-to-digital converter (ADC), and the [Formula: see text] two-stage interleaving structure leads to a good trade-off between bandwidth and linearity. The analysis and cancellation of charge injection, clock feedthrough, and signal feedthrough are presented. Inductor peaking technique is adopted to extend the bandwidth of the buffer between the first and the second stage. Based on the simulation results, the proposed FESC consumes 136[Formula: see text]mW at 32 GS/s, and the signal-to-noise ratio (SNDR) is up to 39.55 dB at Nyquist input, achieving a state-of-the-art power efficiency.

A Time-Interleaved Statistically-Driven Two-Step Flash ADC for High-Speed Wireline Applications

2017 ◽  
Vol 26 (07) ◽  
pp. 1750118 ◽  
Author(s):  
Dengbao Liu ◽  
Lin He ◽  
Fujiang Lin ◽  
Ting Li ◽  
Yu-Kai Chou
Keyword(s):  
Probability Distribution ◽  
Input Signal ◽  
High Speed ◽  
Small Probability ◽  
Flash Adc ◽  
Analog To Digital ◽  
Second Stage ◽  
Large Probability ◽  
Interleaved Adc ◽  
Time Interleaved

This paper presents a statistically-driven two-step flash sub-analog-to-digital converter (ADC) to construct the high-speed time-interleaved ADC in wireline communication applications. The comparators in the flash sub-ADC are divided into the large probability first stage and the small probability second stage to take advantage of the nonuniform probability distribution of the input signal. At the first step of operation, the large probability first stage is activated while the small probability second stage is suspended. If the input signal is beyond the input range of the first stage, the segment selection signal will trigger proper segment in the second stage. Feed-forward equalization is proposed to manipulate the probability distribution of the ADC input signal. A possible implementation of the proposed ADC as well as the modulation and equalization scheme is presented to comply with the IEEE 802.3ap 10[Formula: see text]G Ethernet standard. In the case of a PAM-4 pseudorandom signal, the proposed solution achieves [Formula: see text] reduction on the average number of activated comparators compared to a conventional flash ADC.

scholarly journals Super resolution DOA estimation based on deep neural network

2020 ◽  
Vol 10 (1) ◽  
Author(s):  
Wanli Liu
Keyword(s):  
Neural Network ◽  
Potential Application ◽  
Deep Neural Network ◽  
State Of The Art ◽  
Signal To Noise Ratio ◽  
Super Resolution ◽  
Doa Estimation ◽  
Angular Distance ◽  
Signal To Noise ◽  
Simulation Results

AbstractRecently, deep neural network (DNN) studies on direction-of-arrival (DOA) estimations have attracted more and more attention. This new method gives an alternative way to deal with DOA problem and has successfully shown its potential application. However, these works are often restricted to previously known signal number, same signal-to-noise ratio (SNR) or large intersignal angular distance, which will hinder their generalization in real application. In this paper, we present a novel DNN framework that realizes higher resolution and better generalization to random signal number and SNR. Simulation results outperform that of previous works and reach the state of the art.

scholarly journals PROGRAMMABLE PARALLEL FBD SIGMA DELTA ADC RECONSTRUCTION STAGE DESIGN FOR SOFTWARE DEFINED RADIO RECEIVER

2016 ◽  
pp. 14-21
Author(s):  
Rihab Lahouli ◽  
Manel Ben-Romdhane ◽  
Chiheb Rebai ◽  
Dominique Dallet
Keyword(s):  
Software Defined Radio ◽  
Signal To Noise Ratio ◽  
Parallel Architecture ◽  
Use Case ◽  
Sigma Delta ◽  
Analog To Digital ◽  
Sigma Delta Modulators ◽  
Digital Reconstruction ◽  
Simulation Results ◽  
Sigma Delta Adc

Today’s bottleneck of signal processing in multistandard software defined radio (SDR) receiver is the analog-to-digital converter (ADC). Therefore, the authors present in this paper the design and simulation results of a programmable parallel frequency band decomposition (FBD) architecture for ADC. The designed parallel architecture is composed of six parallel branches based on discrete-time (DT) 4th order sigma delta modulators using single-bit quantizers. Each branch processes a sub-bandwidth of the received signal. Only needed branches are selected according to the chosen standard. The parallel sigma delta modulators’ outputs are handled by a demodulation-based digital reconstruction stage in order to provide the FBD sigma delta-based ADC output signal. The digital reconstruction stage differs from one communication standard to another. In this paper, its design is discussed for the UMTS use case. The objective is to propose a digital reconstruction design with optimized complexity. In fact, the authors propose a comparative study between some configurations of demodulation, decimation and filtering processes. Technical choices and simulation results are discussed. For UMTS use case, the proposed FBD sigma delta-based ADC architecture ensures a computed signal-to-noise ratio (SNR) over 74 dB.

Low power front-end architecture dedicated to the multistandard simultaneous reception

2010 ◽  
Vol 2 (6) ◽  
pp. 505-514 ◽  
Author(s):  
Ioan Burciu ◽  
Guillaume Villemaud ◽  
Jacques Verdier ◽  
Matthieu Gautier
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Signal To Noise Ratio ◽  
Mobile Telecommunications ◽  
Signal To Noise ◽  
Front End ◽  
Analog Front End ◽  
Universal Mobile Telecommunications System ◽  
Study Case ◽  
Simulation Results

In this paper, we address the architecture of multistandard simultaneous reception receivers and we aim to reduce the complexity and the power consumption of the analog front-end. To this end, we propose an architecture using the double orthogonal translation technique in order to multiplex two signals received on different frequency bands. A study case concerning the simultaneous reception of 802.11 g and Universal Mobile Telecommunications System (UMTS) signals is developed in this article. Theoretical and simulation results show that this type of multiplexing does not significantly influence the evolution of the signal-to-noise ratio of the signals. In the same time a 30% reduction of the power consumption is expected as well as a significant reduction of the complexity.

A LOW-POWER LOW-VOLTAGE 6-BIT 1.33 GS/s FULLY MCML ALL NMOS FLASH ADC WITHOUT A FRONT-END T/H

2013 ◽  
Vol 22 (08) ◽  
pp. 1350074 ◽  
Author(s):  
SARA NESHANI ◽  
SEYED JAVAD AZHARI
Keyword(s):  
Low Power ◽  
Power Efficiency ◽  
Low Voltage ◽  
Current Mode ◽  
Flash Adc ◽  
Analog To Digital ◽  
Current Mode Logic ◽  
Front End ◽  
Compact Size ◽  
Nmos Transistors

In this work, a 6-bit 1.33 GS/s flash analog-to-digital converter (ADC) is proposed. To noticeably save the power and area and greatly increase the speed, compactness and accuracy its complete structure is elaborately implemented in MOS Current Mode Logic (MCML) topology. The proposed ADC does not use a front-end track and hold (T/H) block either. Furthermore, a novel optimized resistance ratio averaging-interpolation scheme is applied to: (1) reduce the offset, nonlinearity, number of preamplifiers, area and the power (2) increase the accuracy and mismatch insensitivity (3) minimize the size of elements towards the more compact size, smaller area and higher speed for the ADC. To maximize all these achievements, most favorably, it is completely built by NMOS transistors realizing the ever desired unique NMCML (NMOS-MCML) structure. Using intermediate gray encoding and exponential gains by extra latches greatly removes the bubble/meta-stability error and increases both the speed and the accuracy. Utilizing a differential ladder and some other deliberate arrangements reduces the kickback noise and common mode interferences, minimizes the structure and facilitates fast recovery of overdrive signals. The proposed ADC is simulated by Hspice using 0.18 μm TSMC technology and shows; effective resolution band width (ERBW) larger than 903 MHz that is 1.36 times more than Nyquist frequency (fs/2), 35.17 dB/49.4 dB SNDR/SFDR, 5.53 bits ENOB (rather flat SNDR and ENOB from 50 MHz to 750 MHz), and the low power consumption of 37.77 mW from a 1.2 V supply. These results prove that applying so many effective and novel plans has obtained a unique all N-MCML flash ADC with power-efficiency of 0.61 pJ per conversion step. Both Monte Carlo and corner cases simulations in addition to temperature analysis are performed that prove both intra-die and inter-die robustness of the proposed structure.

A Review on Calibration Methods of Timing-Skew in Time-Interleaved ADCs

2019 ◽  
Vol 29 (02) ◽  
pp. 2030002
Author(s):  
Xin Li ◽  
Cheng Huang ◽  
Desheng Ding ◽  
Jianhui Wu
Keyword(s):  
State Of The Art ◽  
Time Interleaving ◽  
Analog To Digital ◽  
Systematic Overview ◽  
Current State ◽  
Calibration Methods ◽  
Overall Performance ◽  
Time Interleaved ◽  
Statistical Results ◽  
Timing Skew

Time-interleaving has been a popular choice for multi-GHz analog-to-digital converters (ADCs) with a resolution of 8–14 bits. Unfortunately, inherent defects such as offset, gain, timing-skew mismatches among sub-ADCs degrade overall performance seriously. At present, the method for eliminating offset and gain mismatch is fairly straightforward; however, calibration for timing-skew is still in a state of exploration. A systematic overview of various calibration methods for timing-skew in time-interleaved ADCs (TI-ADCs) has been provided in this paper. Meanwhile, current state-of-the-art TI-ADCs recently are reported and several noteworthy trends can be observed from the statistical results.

HIGH-SPEED OVERSAMPLING ANALOG-TO-DIGITAL CONVERTERS

2005 ◽  
Vol 15 (02) ◽  
pp. 297-317 ◽  
Author(s):  
AHMED GHARBIYA ◽  
TREVOR C. CALDWELL ◽  
D. A. JOHNS
Keyword(s):  
Discrete Time ◽  
Input Signal ◽  
Continuous Time ◽  
High Frequency ◽  
High Speed ◽  
State Of The Art ◽  
Analog To Digital Converters ◽  
Analog To Digital ◽  
Time Interleaved

This paper is mainly tutorial in nature and discusses architectures for oversampling converters with a particular emphasis on those which are well suited for high frequency input signal bandwidths. The first part of the paper looks at various architectures for discrete-time modulators and looks at their performance when attempting high speed operation. The second part of this paper presents some recent advancements in time-interleaved oversampling converters. The next section describes the design and challenges in continuous-time modulators. Finally, conclusions are made and a brief summary of the recent state of the art of high-speed converters is presented.

Upgrading an Analog Recovery Loop for Optimized Decoding Jointly to an Increased data-Rate

2021 ◽  
Author(s):  
Giuseppe Visalli
Keyword(s):  
Signal To Noise Ratio ◽  
Signal To Noise ◽  
Output Data ◽  
Analog To Digital ◽  
Soft Decoding ◽  
Maximum Likelihood Detection ◽  
Wireless Applications ◽  
Log Likelihood ◽  
Simulation Results ◽  
Alternate Solution

Abstract The maximum likelihood detection theory improves the error-rate of a sub-optimal but cheaper, coded symbol recovery loop using oversampling proposed as an alternate solution for the decoding problem without the log-likelihood ratio computation. The former implementation delivers the output data in one-symbol delay, and the required transistor count makes this approach attractive for ultra-low-energy wireless applications. The proposed hardware upgrade includes an analog to digital converter and fixed-point accumulation logic to compute the soft values, replacing a trigger used as a hard detector. This work investigates the soft decoding in the presence of binary and non-binary source symbols. Simulation results show that the soft approach improves the signal-to-noise ratio by 3dB and 2.5 dB when the encoding rates are 1/3 and 2/3.

An 8-Bit 0.333–2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS

2015 ◽  
Vol 24 (06) ◽  
pp. 1550093 ◽  
Author(s):  
Dengquan Li ◽  
Liang Zhang ◽  
Zhangming Zhu ◽  
Yintang Yang
Keyword(s):  
Single Channel ◽  
Mode Selection ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Analog To Digital ◽  
Timing Errors ◽  
Delay Locked Loop ◽  
Simulation Results ◽  
On Chip ◽  
Time Interleaved

This paper presents an 8-bit configurable time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). By using a mode selection circuit, four modes of sampling rate are provided: Single channel at 333.3 MS/s, 2-channel at 666.7 MS/s, 3-channel at 1 GS/s and 6-channel at 2 GS/s. An on-chip delay-locked loop (DLL) uniformly generates six-phase clock with 20% duty cycle, and the timing errors are reduced to a tolerable range. In low sampling rate modes, the corresponding sampling switches and comparators in the idle sub-ADCs are shut down to save power consumption. Based on the 65-nm CMOS technology, the post-layout simulation results show that at 1.2 V supply, the proposed ADC consumes 8.6, 10.9, 13.1 and 19.9 mW under different modes. With an ENOB of 7.92, 7.34, 7.01 and 6.37 bit, this results in a FOM of 106.6, 100.9, 101.6 and 120.3 fJ/conversion-step respectively.

Design Technique of High Power Efficiency LLC DC-DC Converters for Photovoltaic Cells

2018 ◽  
Vol 2 (1) ◽  
pp. 30
Author(s):  
Hisatsugu Kato ◽  
Yoichi Ishizuka ◽  
Kohei Ueda ◽  
Shotaro Karasuyama ◽  
Atsushi Ogasahara
Keyword(s):  
High Power ◽  
Power Efficiency ◽  
Photovoltaic Cells ◽  
Input Voltage ◽  
Design Technique ◽  
Load Range ◽  
Voltage Range ◽  
Simulation Results ◽  
Secondary Side ◽  
High Power Efficiency

This paper proposes a design technique of high power efficiency LLC DC-DC Converters for Photovoltaic Cells. The secondary side circuit and transformer fabrication of proposed circuit are optimized for overcoming the disadvantage of limited input voltage range and, realizing high power efficiency over a wide load range of LLC DC-DC converters. The optimized technique is described with theoretically and with simulation results. Some experimental results have been obtained with the prototype circuit designed for the 80 - 400 V input voltage range. The maximum power efficiency is 98 %.

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